Over the two decades, amorphous oxide semiconductors (AOSs) and their thin film transistor (TFT) channel application have been intensely explored to realize high performance, transparent and flexible displays due to their high field effect mobility (μFE=5-20 cm2/Vs), visible range optical transparency, and low temperature processability (25-300 °C).[1-2] The metastable amorphous phase is to be maintained during operation by the addition of Zn and additional third cation species (e.g., Ga, Hf, or Al) as an amorphous phase stabilizer.[3-5] To limit TFT off-state currents, a thin channel layer (10-20 nm) was employed for InZnO (IZO)-based TFTs, or third cations were added to suppress carrier generations in the TFT channel. To resolve bias stress-induced instabilities in TFT performance, approaches to employ defect passivation layers or enhance channel/dielectric interfacial compatibility were demonstrated.[6-7]
Metallization contact is also a dominating factor that determines the performance of TFTs. Particularly, it has been reported that high electrical contact resistance significantly sacrifices drain bias applied to the channel, which leads to undesirable power loss during TFT operation and issues for the measurement of TFT field effect mobilities. [2, 8] However, only a few reports that suggest strategies to enhance contact behaviors are available in the literature. Furthermore, the previous approaches (1) require an additional fabrication complexity due to the use of additional treatments at relatively harsh conditions such as UV, plasma, or high temperatures, and (2) may lead to adverse effects on the channel material attributed to the chemical incompatibility between dissimilar materials, and exposures to harsh environments. Therefore, a simple and easy but effective buffer strategy, which does not require any additional process complexities and not sacrifice chemical compatibility, needs to be established to mitigate the contact issues and therefore achieve high performance and low power consumption AOS TFTs.
The present study aims to demonstrate an approach utilizing an interfacial buffer layer, which is compositionally homogeneous to the channel to better align work functions between channel and metallization without a significant fabrication complexity and harsh treatment conditions. Photoelectron spectroscopic measurements reveal that the conducting IZO buffer, of which the work function (Φ) is 4.37 eV, relaxes a relatively large Φ difference between channel IZO (Φ=4.81 eV) and Ti (Φ=4.2-4.3 eV) metallization. The buffer is found to lower the energy barrier for charge carriers at the source to reach the effective channel region near the dielectric. In addition, the higher carrier density of the buffer and favorable chemical compatibility with the channel (compositionally the same) further contribute to a significant reduction in specific contact resistance as much as more than 2.5 orders of magnitude. The improved contact and carrier supply performance from the source to the channel lead to an enhanced field effect mobility of up to 56.49 cm2/Vs and a threshold voltage of 1.18 V, compared to 13.41 cm2/Vs and 7.44 V of IZO TFTs without a buffer. The present work is unique in that an approach to lower the potential barrier between the source and the effective channel region (located near the channel/dielectric interface, behaving similar to a buried-channel MOSFET [9]) by introducing a contact buffer layer that enhances the field effect mobility and facilitates carrier supply from the source to the effective channel region.
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The role of third cation doping on phase stability, carrier transport and carrier suppression in amorphous oxide semiconductors
Amorphous oxide semiconductors (AOSs), specifically those based on ternary cation systems such as Ga-, Si-, and Hf-doped InZnO, have emerged as promising material candidates for application in next-gen transparent electronic and optoelectronic devices. Third cation-doping is a common method used during the manufacturing of amorphous oxide thin film transistors (TFTs), primarily with the intention of suppressing carrier generation during the fabrication of the channel layer of a transistor. However, the incorporation of a third cation species has been observed to negatively affect the carrier transport properties of the thin film, as it may act as an additional scattering center and subsequently lower the carrier mobility from ∼20–40 cm 2 V −1 s −1 of In 2 O 3 or a binary cation system ( i.e. , InZnO) to ∼1–10 cm 2 V −1 s −1 . This study investigates the structural, electrical, optoelectronic, and chemical properties of the ternary cation material system, InAlZnO (IAZO). The optimized carrier mobility (Hall Effect) of Al-doped InZnO is shown to remain as high as ∼25–45 cm 2 V −1 s −1 . Furthermore, Al incorporation in InZnO proves to enhance the amorphous phase stability under thermal stresses when compared to baseline InZnO films. Thin film transistors integrating optimized IAZO as the channel layer are shown to demonstrate promisingly high field effect mobilities (∼18–20 cm 2 V −1 s −1 ), as well as excellent drain current saturation and high drain current on/off ratios (>10 7 ). The high mobility and improved amorphous phase stability suggest strong potential for IAZO incorporation in the next generation of high performance and sustainable optoelectronic devices such as transparent displays.
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- Award ID(s):
- 1931088
- NSF-PAR ID:
- 10289742
- Date Published:
- Journal Name:
- Journal of Materials Chemistry C
- Volume:
- 8
- Issue:
- 39
- ISSN:
- 2050-7526
- Page Range / eLocation ID:
- 13798 to 13810
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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The discovery of oxide electronics is of increasing importance today as one of the most promising new technologies and manufacturing processes for a variety of electronic and optoelectronic applications such as next-generation displays, batteries, solar cells, memory devices, and photodetectors[1]. The high potential use seen in oxide electronics is due primarily to their high carrier mobilities and their ability to be fabricated at low temperatures[2]. However, since the majority of oxide semiconductors are n-type oxides, current applications are limited to unipolar devices, eventually developing oxide-based bipolar devices such as p-n diodes and complementary metal-oxide semiconductors. We have contributed to a wide range of oxide semiconductors and their electronics and optoelectronic device applications. Particularly, we have demonstrated n-type oxide-based thin film transistors (TFT), integrating In 2 O 3 -based n-type oxide semiconductors from binary cation materials to ternary cation species including InZnO, InGaZnO (IGZO), and InAlZnO. We have suggested channel/metallization contact strategies to achieve stable and high TFT performance[3, 4], identified vacancy-based native defect doping mechanisms[5], suggested interfacial buffer layers to promote charge injection capability[6], and established the role of third cation species on the carrier generation and carrier transport[7]. More recently, we have reported facile manufacturing of p-type SnOx through reactive magnetron sputtering from a Sn metal target[8]. The fabricated p-SnOx was found to be devoid of metallic phase of Sn from x-ray photoelectron spectroscopy and demonstrated stable performance in a fully oxide-based p-n heterojunction together with n-InGaZnO. The oxide-based p-n junctions exhibited a high rectification ratio greater than 10 3 at ±3 V, a low saturation current of ~2x10 -10 , and a small turn-on voltage of -0.5 V. In this presentation, we review recent achievements and still remaining issues in transition metal oxide semiconductors and their device applications, in particular, bipolar applications including p-n heterostructures and complementary metal-oxide-semiconductor devices as well as single polarity devices such as TFTs and memristors. In addition, the fundamental mechanisms of carrier transport behaviors and doping mechanisms that govern the performance of these oxide-based devices will also be discussed. ACKNOWLEDGMENT This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS. K.N. was supported by Basic Science Research Program (NRF-2021R11A1A01051246) through the NRF Korea funded by the Ministry of Education. REFERENCES [1] K. Nomura et al. , Nature, vol. 432, no. 7016, pp. 488-492, Nov 25 2004. [2] D. C. Paine et al. , Thin Solid Films, vol. 516, no. 17, pp. 5894-5898, Jul 1 2008. [3] S. Lee et al. , Journal of Applied Physics, vol. 109, no. 6, p. 063702, Mar 15 2011, Art. no. 063702. [4] S. Lee et al. , Applied Physics Letters, vol. 104, no. 25, p. 252103, 2014. [5] S. Lee et al. , Applied Physics Letters, vol. 102, no. 5, p. 052101, Feb 4 2013, Art. no. 052101. [6] M. Liu et al. , ACS Applied Electronic Materials, vol. 3, no. 6, pp. 2703-2711, 2021/06/22 2021. [7] A. Reed et al. , Journal of Materials Chemistry C, 10.1039/D0TC02655G vol. 8, no. 39, pp. 13798-13810, 2020. [8] D. H. Lee et al. , ACS Applied Materials & Interfaces, vol. 13, no. 46, pp. 55676-55686, 2021/11/24 2021.more » « less
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The discovery of oxide electronics is of increasing importance today as one of the most promising new technologies and manufacturing processes for a variety of electronic and optoelectronic applications such as next-generation displays, batteries, solar cells, and photodetectors. The high potential use seen in oxide electronics is due primarily to their high carrier mobilities and their ability to be fabricated at low temperatures. However, since the majority of oxide semiconductors are n-type oxides, current applications are limited to unipolar devices, eventually developing oxide-based bipolar devices such as p-n diodes and complementary metal-oxide semiconductors. We have contributed to wide range of oxide semiconductors and their electronics and optoelectronic device applications. Particularly, we have demonstrated n-type oxide-based thin film transistors (TFT), integrating In2O3-based n-type oxide semiconductors from binary cation materials to ternary cation species including InZnO, InGaZnO (IGZO), and InAlZnO. We have suggested channel/metallization contact strategies to achieve stable TFT performance, identified vacancy-based native defect doping mechanisms, suggested interfacial buffer layers to promote charge injection capability, and established the role of third cation species on the carrier generation and carrier transport. More recently, we have reported facile manufacturing of p-type SnOx through reactive magnetron sputtering from a Sn metal target. The fabricated p-SnOx was found to be devoid of metallic phase of Sn from x-ray photoelectron spectroscopy and demonstrated stable performance in a fully oxide based p-n heterojunction together with n-InGaZnO. The oxide-based p-n junctions exhibited a high rectification ratio greater than 103 at ±3 V, a low saturation current of ~2x10-10, and a small turn-on voltage of -0.5 V. With all the previous achievements and investigations about p-type oxide semiconductors, challenges remain for implementing p-type oxide realization. For the implementation of oxide-based p-n heterojunctions, the performance needs to be further enhanced. The current on/off ration may be limited, in our device structure, due to either high reverse saturation current (or current density) or non-ideal performance. In this study, two rational strategies are suggested to introduce an “intrinsic” layer, which is expected to reduce the reverse saturation current between p-SnOx and n-IGZO and hence increase the on/off ratio. The carrier density of n-IGZO is engineered in-situ during the sputtering process, by which compositionally homogeneous IGZO with significantly reduced carrier density is formed at the interface. Then, higher carrier density IGZO is formed continuously on the lower carrier density IGZO during the sputtering process without any exposure of the sample to the air. Alternatively, heterogeneous oxides of MgO and SiO2 are integrated into between p-SnOx and n-IGZO, by which the defects on the surface can be passivated. The interfacial properties are thoroughly investigated using transmission electron microscopy and atomic force microscopy. The I-V characteristics are compared between the set of devices integrated with two types of “intrinsic” layers. The current research results are expected to contribute to the development of p-type oxides and their industrial application manufacturing process that meets current processing requirements, such as mass production in p-type oxide semiconductors.more » « less
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Abstract New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of line manufacturing are needed for 3D monolithic integration of thin‐film electronics. Here, three atomic layer deposition (ALD) processes are compared for the fabrication of amorphous zinc tin oxide (ZTO) channels in bottom‐gate, top‐contact n‐channel transistors. As‐deposited ZTO films, made by ALD at 150–200 °C, exhibit semiconducting, enhancement‐mode behavior with electron mobility as high as 13 cm2V−1s−1, due to a low density of oxygen‐related defects. ZTO deposited at 200 °C using a hybrid thermal‐plasma ALD process with an optimal tin composition of 21%, post‐annealed at 400 °C, shows excellent performance with a record high mobility of 22.1 cm2V–1s–1and a subthreshold slope of 0.29 V dec–1. Increasing the deposition temperature and performing post‐deposition anneals at 300–500 °C lead to an increased density of the X‐ray amorphous ZTO film, improving its electrical properties. By optimizing the ZTO active layer thickness and using a high‐
k gate insulator (ALD Al2O3), the transistor switching voltage is lowered, enabling electrical compatibility with silicon integrated circuits. This work opens the possibility of monolithic integration of ALD ZTO‐based thin‐film electronics with silicon integrated circuits or onto large‐area flexible substrates. -
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Additive patterning of transparent conducting metal oxides at low temperatures is a critical step in realizing low‐cost transparent electronics for display technology and photovoltaics. In this work, inkjet‐printed metal oxide transistors based on pure aqueous chemistries are presented. These inks readily convert to functional thin films at lower processing temperatures (
T ≤ 250 °C) relative to organic solvent‐based oxide inks, facilitating the fabrication of high‐performance transistors with both inkjet‐printed transparent electrodes of aluminum‐doped cadmium oxide (ACO) and semiconductor (InOx ). The intrinsic fluid properties of these water‐based solutions enable the printing of fine features with coffee‐ring free line profiles and smoother line edges than those formed from organic solvent‐based inks. The influence of low‐temperature annealing on the optical, electrical, and crystallographic properties of the ACO electrodes is investigated, as well as the role of aluminum doping in improving these properties. Finally, the all‐aqueous‐printed thin film transistors (TFTs) with inkjet‐patterned semiconductor (InOx ) and source/drain (ACO) layers are characterized, which show ideal low contact resistance (R c< 160 Ω cm) and competitive transistor performance (µ linup to 19 cm2V−1s−1, Subthreshold Slope (SS) ≤150 mV dec−1) with only low‐temperature processing (T ≤ 250 °C).
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- Journal Article:
- https://doi.org/10.1039/D0TC02655G
