An official website of the United States government
With the expansion of sensor nodes to newer avenues of technologies, such as the Internet of things (IoT), internet of bodies (IoB), augmented reality (AR), and mixed reality, the demand to support high-speed operations, such as audio and video, with a minimal increase in power consumption is gaining much traction. In this work, we focus on these nodes operating in audio-based AR (AAR) and explore the opportunity of supporting audio at a low power budget. For sensor nodes, communicating one bit of data usually consumes significantly higher power than the power associated with sensing and processing/computing one data bit. Compressing the number of communication bits at the expense of a few computation cycles considerably reduces the overall power consumption of the nodes. Audio codecs such as AAC and LDAC that currently perform compression and decompression of audio streams burn significant power and create a floor to the minimum power possible in these applications. Compressive sensing (CS), a powerful mathematical tool for compression, is often used in physiological signal sensing, such as EEG and ECG, and it can offer a promising low-power alternative to audio codecs. We introduce a new paradigm of using the CS-based approach to realize audio compression that can function as a new independent technique or augment the existing codecs for a higher level of compression. This work, CS-Audio, fabricated in TSMC 65-nm CMOS technology, presents the first CS-based compression, equipped with an ON-chip DWT sparsifier for non-sparse audio signals. The CS design, realized in a pipelined architecture, achieves high data rates and enables a wake-up implementation to bypass computation for insignificant input samples, reducing the power consumption of the hardware. The measurement results demonstrate a 3X-15X reduction in transmitted audio data without a perceivable degradation of audio quality, as indicated by the perceptual evaluation of audio quality mean opinion score (PEAQ MOS) >1.5. The hardware consumes 238 μW power at 0.65 V and 15 Mbps, which is (~20X-40X) lower than audio codecs.
more »
« less
A Low-Power Front-End with Compressive Sensing Circuit for Neural Signal Acquisition Designed in 180 nm CMOS Process
Multi-channel data acquisition of bio-signals is a promising technology that is being used in many fields these days. Compressed sensing (CS) is an innovative approach of signal processing that facilitates sub-Nyquist processing of bio-signals, such as an electrocardiogram (ECG) and electroencephalogram (EEG). This strategy can be used to lower the data rate to realize ultra-low-power performance, As the count of recording channels increase, data volume is increased resulting in impermissible transmitting power. This paper presents the implementation of a CMOS-based front-end design with the CS in the standard 180 nm CMOS process. A novel pseudo-random sequence generator is proposed, which consists of two different types of D flip-flops that are used for obtaining a completely random sequence. The power consumed by the bio-signal amplifier block is 2.35 μW. The SAR-ADC block that is designed to digitize the amplified signal consumes 277 μW of power and the power consumption value of the pseudo-random bit sequence generator (PRBS) is 344.2μW. The sampling rate of PRBS block is 611.76 Kbps. We have considered collecting neural data from the 32 channels, and achieved an 8.5X compression rate. The low power consumption per channel confirms the importance of the proposed approach for multiple channel high-density neural interfaces.
more »
« less
- Award ID(s):
- 1943990
- PAR ID:
- 10314080
- Date Published:
- Journal Name:
- 2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.more » « less
-
We report a power-efficient analog front-end integrated circuit (IC) for multi-channel, dual-band subcortical recordings. In order to achieve high-resolution multi-channel recordings with low power consumption, we implemented an incremental ΔΣ ADC (IADC) with a dynamic zoom-and-track scheme. This scheme continuously tracks local field potential (LFP) and adaptively adjusts the input dynamic range (DR) into a zoomed sub-LFP range to resolve tiny action potentials. Thanks to the reduced DR, the oversampling rate of the IADC can be reduced by 64.3% compared to the conventional approach, leading to significant power reduction. In addition, dual-band recording can be easily attained because the scheme continuously tracks LFPs without additional on-chip hardware. A prototype four-channel front-end IC has been fabricated in 180 nm standard CMOS processes. The IADC achieved 11.3-bit ENOB at 6.8 μW, resulting in the best Walden and SNDR FoMs, 107.9 fJ/c-s and 162.1 dB, respectively, among two different comparison groups: the IADCs reported up to date in the state-of-the-art neural recording front-ends; and the recent brain recording ADCs using similar zooming or tracking techniques to this work. The intrinsic dual-band recording feature reduces the post-processing FPGA resources for subcortical signal band separation by >45.8%. The front-end IC with the zoom-and-track IADC showed an NEF of 5.9 with input-referred noise of 8.2 μVrms, sufficient for subcortical recording. The performance of the whole front-end IC was successfully validated through in vivo animal experiments.more » « less
-
The Hilbert transform is widely used in biomedical signal processing and requires efficient implementation. We propose the implementation of the discrete Hilbert transform based on emerging memristor devices. It uses two matrix multiplication layers using weights programmed in the memristor array and a linear Hadamard product calculation layer mappable to CMOS. The functionality was tested on a dataset of optical cardiac signals from the human heart. The results show negligible <1% angle error between the proposed implementation and the MATLAB function. It also has robustness to non-idealities. This proposed solution can be applied to bio-signal processing at the edge.more » « less
-
Wearable devices typically use electromagnetic fields for wireless information exchange. For implanted devices, electromagnetic signals suffer from a high amount of absorption in tissue, and alternative modes of transmission (ultrasound, optical and magneto-electric) cause large transduction losses due to energy conversion. To mitigate this challenge, we report biphasic quasistatic brain communication for wireless neural implants. The approach is based on electro-quasistatic signalling that avoids transduction losses and leads to an end-to-end channel loss of only around 60 dB at a distance of 55 mm. It utilizes dipole-coupling-based signal transfer through the brain tissue via differential excitation in the transmitter (implant) and differential signal pickup at the receiver (external hub). It also employs a series capacitor before the signal electrode to block d.c. current flow through the tissue and maintain ion balance. Since the electrical signal transfer through the brain is electro-quasistatic up to the several tens of megahertz, it provides a scalable (up to 10 Mbps), low-loss and energy-efficient uplink from the implant to an external wearable. The transmit power consumption is only 0.52 μW at 1 Mbps (with 1% duty cycling)—within the range of possible energy harvesting in the downlink from a wearable hub to an implant.more » « less
- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/DCAS51144.2020.9330674
