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1. HSC-FPGA: A Hybrid Spin/Charge FPGA Leveraging the Cooperating Strengths of CMOS and MTJ Devices

   Zand, Ramtin ; DeMara, Ronald F. ( February 2019 , Field-programmable gate arrays)

   The HSC-FPGA offers an intriguing feasible architecture for the next generation of configurable fabrics, which allows embracing the advantages of both CMOS and beyond-CMOS technologies without requiring significant modification to the routing structure, programming paradigms, and synthesis tool-chain of the commercial FPGAs. In the HSC-FPGA, the intrinsic characteristics of magnetic random access memory (MRAM)-look-up table (LUT) circuits are used to implement sequential logic, while combinational logic circuits are implemented by static random access memory (SRAM)-LUTs. Fabric-level simulation results for the developed HSC-FPGA show that it can achieve at least 18%, 70%, and 15% reduction in terms of area, standby power, and read power consumption, respectively, for various ISCAS-89 and ITC-99 benchmark circuits compared to conventional SRAM-based FPGAs. The power consumption values can be further decreased by the power-gating allowed by the non-volatility feature of MRAM-LUTs. Moreover, the benefits of increased heterogeneity for reconfigurable computing is extended along realizing probabilistic computing paradigms within a fabric, which is enabled by probabilistic spin logic devices. The cooperating strengths of technology-heterogeneity and heterogeneity in computing paradigm in the proposed HSC-FPGA are leveraged to develop energy-efficient and reliability-aware training and evaluation circuits for deep belief networks with memristive crossbar arrays and p-bit based probabilistic neurons. 

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2. Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement

   https://doi.org/10.1145/2847263.2847334  

   Linscott, Timothy A. ; Gojman, Benjamin ; Rubin, Raphael ; DeHon, Andre ( February 2016 , International Symposium on Field-Programmable Gate Arrays)
3. SALIENT: Ultra-Fast FPGA-based Short Read Alignment

   https://doi.org/10.1109/ICFPT56656.2022.9974548  

   Khaleghi, Behnam ; Zhang, Tianqi ; Martino, Cameron ; Armstrong, George ; Akel, Ameen ; Curewitz, Ken ; Eno, Justin ; Eilert, Sean ; Knight, Rob ; Moshiri, Niema ; et al ( December 2022 , 2022 International Conference on Field-Programmable Technology (ICFPT))
4. Just-In-Time Compilation for Verilog: A New Technique for Improving the FPGA Programming Experience

   https://doi.org/10.1145/3297858.3304010  

   Schkufza, Eric ; Wei, Michael ; Rossbach, Christopher J. ( January 2019 , Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems)

   FPGAs offer compelling acceleration opportunities for modern applications. However compilation for FPGAs is painfully slow, potentially requiring hours or longer. We approach this problem with a solution from the software domain: the use of a JIT. Code is executed immediately in a software simulator, and compilation is performed in the background. When finished, the code is moved into hardware, and from the user's perspective it simply gets faster. We have embodied these ideas in Cascade: the first JIT compiler for Verilog. Cascade reduces the time between initiating compilation and running code to less than a second, and enables generic printf debugging from hardware. Cascade preserves program performance to within 3× in a debugging environment, and has minimal effect on a finalized design. Crucially, these properties hold even for programs that perform side effects on connected IO devices. A user study demonstrates the value to experts and non-experts alike: Cascade encourages more frequent compilation, and reduces the time to produce working hardware designs. 

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5. FPGA-based Reservoir Computing with Optimized Reservoir Node Architecture

   https://doi.org/10.1109/ISQED54688.2022.9806247  

   Lin, Chunxiao ; Liang, Yibin ; Yi, Yang ( April 2022 , 2022 23rd International Symposium on Quality Electronic Design (ISQED))