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1. A phase transition for repeated averages

   https://doi.org/10.1214/21-AOP1526  

   Chatterjee, Sourav; Diaconis, Persi; Sly, Allan; Zhang, Lingfu (January 2022, The Annals of Probability)
2. Design Techniques for a Multi-Phase Injection-Based Eight-Phase 17-GHz Clock Generator for Multi-Phase Wireline Receivers

   https://doi.org/10.1109/TCSI.2025.3563517  

   Zhou, Bob; Nikolić, Borivoje (January 2025, IEEE Transactions on Circuits and Systems I: Regular Papers)

   NA (Ed.)

   Clock generation for high-speed wireline receivers must provide multiple clock phases with high-resolution rotation. To address this, an 8-phase 17 GHz clock generation circuit with built-in 6b rotation is presented. Multi-phase injection is used to perform reference-side phase rotation to efficiently generate and rotate eight clock phases. The injection method is analyzed with a model to study the introduced nonlinearity, and the effect of the injection strength is discussed. Designed by using BAG3++ for layout-aware design optimization, the proposed circuit achieves 98 fs RMS jitter and a measured DNLpp and INLpp of 1.26 and 4.05 LSB respectively, while consuming 33 mW. 

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3. Phase reduction and phase-based optimal control for biological systems: a tutorial

   https://doi.org/10.1007/s00422-018-0780-z  

   Monga, Bharat; Wilson, Dan; Matchen, Tim; Moehlis, Jeff (April 2019, Biological Cybernetics)
4. A Multi-Phase Injection-Locked 8-Phase 17 GHz Clock Generator with 6b Phase Rotation for Multi-Phase Wireline Receivers

   https://doi.org/10.1109/ESSERC62670.2024.10719579  

   Zhou, Bob; Nikolić, Borivoje (September 2024, IEEE)

   A high frequency multi-phase clock generator circuit with a 6b phase rotator is presented for multi-phase wireline receivers. Multi-phase injection is used to efficiently generate and rotate 8 clock phases. Unlike prior rotator-based work, this work does not use time modulation, reducing the resulting deterministic jitter. A model is presented to study the nonlinearity introduced by the technique. The proposed 17 GHz circuit was implemented in the Intel 16 process and consumes 33 mW. The measured RMS jitter is $$\mathbf{9 8} \mathrm{fs}$$, and the measured DNLpp and INLpp are 1.26 and 4.05 LSB respectively. 

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5. A phase-change memory model for neuromorphic computing

   https://doi.org/10.1063/1.5042408  

   Nandakumar, S. R.; Le Gallo, Manuel; Boybat, Irem; Rajendran, Bipin; Sebastian, Abu; Eleftheriou, Evangelos (October 2018, Journal of Applied Physics)