Functional hardware description languages (FHDL) provide powerful tools for building new abstractions that enable sophisticated hardware system to be constructed by composing small reusable parts. Raising the level of abstractions in hardware designs means the programmer can focus on high-level circuit structure rather than mundane low-level details. The language features that facilitate this include high-order functions, rich static type system with type inference, and parametric polymorphism. We use hand-written structural and behavioral VHDL, Simulink, and the Kansas Lava FHDL to re-implement several components taken from a Simulink model of an orthogonal frequency-division multiplexing (OFDM) physical layer (PHY). Our development demonstrates that an FHDL can require fewer lines of code than traditional design languages without sacrificing performance.
more »
« less
An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design
- Award ID(s):
- 1955909
- NSF-PAR ID:
- 10336504
- Date Published:
- Journal Name:
- International Conference on Application-specific Systems, Architectures and Processors
- Page Range / eLocation ID:
- 77 to 84
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
This paper demonstrates a novel, compact-sized hardware-in-the-loop system, and its verification using machine learning and artificial intelligence features in battery controls. Conventionally, a battery management system involves algorithm development for battery modeling, estimation, and control. These tasks are typically validated by running the battery tester open-loop, i.e., the tester equipment executes the pre-defined experimental protocols line by line. Additional equipment is required to make the testing closed-loop, but the integration is typically not straightforward. To improve flexibility and accessibility for battery management, this work proposes a low-cost highly reliable closed-loop charger and discharger. We first focus on the electronic circuit design for battery testing systems to maximize the applied current accuracy and precision. After functional verification, we further investigate applications for closed-loop battery management systems. In particular, we extend the proposed architecture into the learning-based control design, which is a feedback controller. We utilize reinforcement learning techniques to highlight the benefits of closed-loop controls. As an example, we compare this learning-based control strategy with a conventional battery charging control. The experimental results demonstrate that the proposed experimental design is able to handle the learning-based controller and achieve a more reliable and safer charging protocol driven by artificial intelligence.more » « less
-
null (Ed.)Multicores increasingly deploy safety-critical parallel applications that demand resiliency against soft-errors to satisfy the safety standards. However, protection against these errors is challenging due to complex communication and data access protocols that aggressively share on-chip hardware resources. Research has explored various temporal and spatial redundancy-based resiliency schemes that provide multicores with high soft-error coverage. However, redundant execution incurs performance overheads due to interference effects induced by aggressive resource sharing. Moreover, these schemes require intrusive hardware modifications and fall short in providing efficient system availability guarantees. This article proposes PRISM, a resilient multicore architecture that incorporates strong hardware isolation to form redundant clusters of cores, ensuring a non-interference-based redundant execution environment. A soft error in one cluster does not effect the execution of the other cluster, resulting in high system availability. Implementing strong isolation for shared hardware resources, such as queues, caches, and networks requires logic for partitioning. However, it is less intrusive as complex hardware modifications to protocols, such as hardware cache coherence, are avoided. The PRISM approach is prototyped on a real Tilera Tile-Gx72 processor that enables primitives to implement the proposed cluster-level hardware resource isolation. The evaluation shows performance benefits from avoiding destructive hardware interference effects with redundant execution, while delivering superior system availability.more » « less
-
The increasing complexity of System-on-Chip (SoC) designs and the rise of third-party vendors in the semiconductor industry have led to unprecedented security concerns. Traditional formal methods struggle to address software-exploited hardware bugs, and existing solutions for hardware-software co-verification often fall short. This paper presents Microscope, a novel framework for inferring software instruction patterns that can trigger hardware vulnerabilities in SoC designs. Microscope enhances the Structural Causal Model (SCM) with hardware features, creating a scalable Hardware Structural Causal Model (HW-SCM). A domain-specific language (DSL) in SMT-LIB represents the HW-SCM and predefined security properties, with incremental SMT solving deducing possible instructions. Microscope identifies causality to determine whether a hardware threat could result from any software events, providing a valuable resource for patching hardware bugs and generating test input. Extensive experimentation demonstrates Microscope's capability to infer the causality of a wide range of vulnerabilities and bugs located in SoC-level benchmarks.more » « less
- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/ASAP52443.2021.00020
