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Secure memory systems employing AES-CTR encryption face signi! cant performance challenges due to high counter (CTR) cache miss rates, especially in applications with irregular memory access patterns. These high miss rates increase memory tra"c and latency, as each CTR cache miss triggers additional DRAM accesses. To address these bottlenecks and adapt to diverse access patterns, we propose COSMOS (Counter Optimized Secure Memory Operation Scheme), a novel solution leveraging reinforcement learning to reduce long memory access latency. COSMOS integrates two RL-based specialized predictors: one for data location prediction and another for CTR locality prediction, each with a well-de!ned state space, action space, and reward function. The RL-based data location predictor determines whether data reside on-chip or o#- chip after an L1 cache miss, enabling early CTR access for o#-chip predictions with minimal changes to the existing cache hierarchy. The RL-based CTR locality predictor identi!es CTRs with high locality, supporting a locality-centric CTR cache (LCR-CTR) to improve cache e"ciency and reduce miss rates. COSMOS improves performance over MorphCtr by 25% in for irregular memory access applications, with minimal hardware overhead.
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Reducing Load Latency with Cache Level Prediction
High load latency that results from deep cache hierarchies and relatively slow main memory is an important limiter of single-thread performance. Data prefetch helps reduce this latency by fetching data up the hierarchy before it is requested by load instructions. However, data prefetching has shown to be imperfect in many situations. We propose cache-level prediction to complement prefetchers. Our method predicts which memory hierarchy level a load will access allowing the memory loads to start earlier, and thereby saves many cycles. The predictor provides high prediction accuracy at the cost of just one cycle added latency to L1 misses. Level prediction reduces the memory access latency by 20% on average, and provides speedup of 10.3% over a conventional baseline, and 6.1% over a boosted baseline on generic, graph, and HPC applications.
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- Award ID(s):
- 1719061
- PAR ID:
- 10340193
- Date Published:
- Journal Name:
- Proceedings of the 2022 IEEE International Symposium on High Performance Computer Architecture (HPCA)
- Page Range / eLocation ID:
- 648 to 661
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
-
Accepted Manuscript
- Conference Paper:
- https://doi.org/10.1109/HPCA53966.2022.00054
