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Title: Efficient Hardware Implementation of Finite Field Arithmetic AB+C for Binary Ring-LWE Based Post-Quantum Cryptography
Post-quantum cryptography (PQC) has gained significant attention from the community recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from the well-developed quantum computers. The finite field arithmetic AB+C , where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper, we propose a novel hardware implementation of the finite field arithmetic AB+C through three stages of interdependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware architecture is then presented with detailed description; (iii) a thorough implementation has also been given along with the comparison. Overall, (i) the proposed basic structure ( u=1 ) outperforms the existing designs, e.g., it involves 55.9% less area-delay product (ADP) than [13] for n=512 ; (ii) the proposed design also offers very efficient performance in time-complexity and can be used in many future applications.  more » « less
Award ID(s):
2020625
NSF-PAR ID:
10358529
Author(s) / Creator(s):
; ; ;
Date Published:
Journal Name:
IEEE Transactions on Emerging Topics in Computing
Volume:
10
Issue:
1
ISSN:
2376-4562
Page Range / eLocation ID:
1222-1228
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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