skip to main content


Title: An inter-stage filter network for distortion reduction in concurrent dual-band power amplifier operation
This work presents a novel approach for reducing the out-of-band distortion generated in a concurrent dualband power amplifier (PA) without penalty to output power or efficiency using a filter between a driver amplifier and final-stage PA that manipulates the driver amplifier out-of-band distortion such that the overall distortion of the cascade is minimized. The cascaded PA operates at 2.4-GHz and 3.5-GHz with peak output power and drain efficiency of 41.6/40.4 and 65.2/55.1 respectively. The filter reduces the out-of-band distortion of the cascade when excited by dual 10-MHz LTE-like signals by 10 dB while improving average drain efficiency by 5 percentage points.  more » « less
Award ID(s):
1846507
NSF-PAR ID:
10386687
Author(s) / Creator(s):
; ; ;
Date Published:
Journal Name:
IEEE Asia Pacific Microwave Conference
Page Range / eLocation ID:
1-3
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. This work presents a novel power amplifier (PA) architecture employing a feedforward-like loop structure for the linearization of a load-modulated PA. The load-modulating loop combiner (LMLC) is related to a feedforward amplifier, but with the interaction between the main and auxiliary amplifiers to generate both distortion cancellation and load modulation. A brief overview of the underlying theory is presented, followed by a hardware demonstrator operating at 3.5 GHz with 42-dBm peak output power and 55% peak drain efficiency in CW. When excited by a 100-MHz LTE signal, it maintains a 3-ppt EVM improvement and a 2–5-ppt average drain efficiency improvement compared to its standalone main amplifier. 
    more » « less
  2. An analytic theory for dual-input outphasing power amplifiers that incorporate in one unified treatment, the continuum of solutions for power combining including the Doherty and Chireix modes is presented. This unified theory developed at the current-source reference planes reveals the performance trade-off achieved by all of the possible power amplifier (PA) combiners within the continuum of solutions. Furthermore, it identifies a novel type of dual-input hybrid Chireix-Doherty PA that combines key features of the Doherty and Chireix operations such that the fundamental drain voltages applied to both the main and auxiliary transistors remain constant. This hybrid PA relies on an input outphasing angle varying with the input power level to obtain the correct load modulation behavior. A 2-GHz dual-input hybrid Chireix-Doherty PA is implemented using nonlinear embedding and experimentally evaluated to validate the theory. A drain efficiency of 61% at 9-dB backoff power and a maximum output power of about 43 dBm are obtained for continuous-wave (CW) measurements. The efficiency increases monotonously with output power unlike that of the Doherty PA used for comparison. When excited with a 20-MHz LTE signal with 9.5-dB peak-to-average power ratio (PAPR), the dual-input PA yields a 60.0% average drain efficiency and -48.1-dBc adjacent-channel power-leakage ratio (ACLR) after linearization. 
    more » « less
  3. This work presents a power amplifier (PA) linearization approach based on baseband feedback. The modulated signal envelope is fed back from the transistor's drain to its gate with an applied amplitude and phase shift selected to reduce the intermodulation distortion (IMD3) product at the output. The design targets IMD3 improvement near the PA's 1-dB compression point (P1dB), enabling linear operation at a higher output power level and therefore improved device periphery utilization and efficiency. This approach offers a potential linearization alternative to digital pre-distortion, which cannot be applied in some systems, without affecting the RF performance. The 850-MHz proof-of-concept prototype based on a 15-W GaN device is characterized with a two-tone measurement with 5-MHz spacing, and demonstrates 9-dB improvement of the lower IMD3 tone near the P1dB point. 
    more » « less
  4. The challenges associated with efficiently and effectively linearizing a nonlinear power amplifier (PA) over wide signal bandwidths are increasingly important to the design of 5G front-ends. Conventional digital linearization techniques are limited by absolute bandwidth, while the RF-domain nonlinear PA typically exhibits consistent fractional bandwidth even as the carrier frequency is increased. Therefore, RF-domain design techniques, like those focusing on bias-line impedance selection, are critical for overall distortion reduction. To evaluate bias-line effects, a demonstrator PA is here investigated over a range of Class-AB biases and over a range of drain inductance values. The characterization under two-tone and LTE-like modulated excitations with 10-MHz and 100-MHz instantaneous bandwidth shows that the conventional linear-efficiency trade-off in bias design does not necessarily hold true for wide instantaneous bandwidths. Additionally, techniques to synthesize a negative baseband impedance using low frequency feedback are discussed. 
    more » « less
  5. This is the first report of a distributed amplifier (DA) realized through monolithic integration of transistors with a substrate-integrated waveguide (SIW). The DA uses a steppedimpedance microstrip line as the input divider like in conventional DAs, but uses a low-loss, high-power-capacity SIW as the output combiner. The input signal is distributed to four GaN high-electron mobility transistors (HEMTs) evenly in magnitude but with the phase successively delayed by 90° at the fundamental frequency. The HEMTs are separated by a half wavelength at the second harmonic frequency in the SIW, so that their outputs are combined coherently at the SIW output. To overcome the limited speed of the GaN HEMTs, they are driven nonlinearly to generate second harmonics, and their fundamental outputs are suppressed with the SIW acting as a high-pass filter. The measured characteristics of the DA agree with that simulated at the small-signal level, but exceeds that simulated at the large-signal level. For example, under an input of 68 GHz and 10 dBm, the output at 136 GHz is 24-dB above the fundamental. Under an input of 68 GHz and 20 dBm, the output at 136 GHz is 14 dBm, with a conversion loss of 6 dB and a power consumption of 882 mW. This proof-of-principle demonstration opens the path to improving the gain, power and efficiency of DAs with higher-performance transistors and drive circuits. Although the demonstration is through monolithic integration, the approach is applicable to heterogeneous integration with the SIW and transistors fabricated on separate chips. 
    more » « less