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1. Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator

   https://doi.org/10.1145/3287624.3287715  

   Lin, Jilan; Zhu, Zhenhua; Wang, Yu; Xie, Yuan (January 2019, the 24th Asia and South Pacific Design Automation Conference)
2. GraphR: Accelerating Graph Processing Using ReRAM

   https://doi.org/10.1109/HPCA.2018.00052  

   Song, Linghao; Zhuo, Youwei; Qian, Xuehai; Li, Hai; Chen, Yiran (February 2018, IEEE International Symposium on High Performance Computer Architecture (HPCA))

   Graph processing recently received intensive interests in light of a wide range of needs to understand relationships. It is well-known for the poor locality and high memory bandwidth requirement. In conventional architectures, they incur a significant amount of data movements and energy consumption which motivates several hardware graph processing accelerators. The current graph processing accelerators rely on memory access optimizations or placing computation logics close to memory. Distinct from all existing approaches, we leverage an emerging memory technology to accelerate graph processing with analog computation. This paper presents GRAPHR, the first ReRAM-based graph processing accelerator. GRAPHR follows the principle of near-data processing and explores the opportunity of performing massive parallel analog operations with low hardware and energy cost. The analog computation is suitable for graph processing because: 1) The algorithms are iterative and could inherently tolerate the imprecision; 2) Both probability calculation (e.g., PageRank and Collaborative Filtering) and typical graph algorithms involving integers (e.g., BFS/SSSP) are resilient to errors. The key insight of GRAPHR is that if a vertex program of a graph algorithm can be expressed in sparse matrix vector multiplication (SpMV), it can be efficiently performed by ReRAM crossbar. We show that this assumption is generally true for a large set of graph algorithms. GRAPHR is a novel accelerator architecture consisting of two components: memory ReRAM and graph engine (GE). The core graph computations are performed in sparse matrix format in GEs (ReRAM crossbars). The vector/matrix-based graph computation is not new, but ReRAM offers the unique opportunity to realize the massive parallelism with unprecedented energy efficiency and low hardware cost. With small subgraphs processed by GEs, the gain of performing parallel operations overshadows the wastes due to sparsity. The experiment results show that GRAPHR achieves a 16.01X (up to 132.67X) speedup and a 33.82X energy saving on geometric mean compared to a CPU baseline system. Compared to GPU, GRAPHR achieves 1.69X to 2.19X speedup and consumes 4.77X to 8.91X less energy. GRAPHR gains a speedup of 1.16X to 4.12X, and is 3.67X to 10.96X more energy efficiency compared to PIM-based architecture. 

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3. ReRAM-based accelerator for deep learning

   https://doi.org/10.23919/DATE.2018.8342118  

   Li, Bing; Song, Linghao; Chen, Fan; Qian, Xuehai; Chen, Yiran; Li, Hai Helen (March 2018, Design, Automation and Test in Europe Conference & Exhibition (DATE))

   Big data computing applications such as deep learning and graph analytic usually incur a large amount of data movements. Deploying such applications on conventional von Neumann architecture that separates the processing units and memory components likely leads to performance bottleneck due to the limited memory bandwidth. A common approach is to develop architecture and memory co-design methodologies to overcome the challenge. Our research follows the same strategy by leveraging resistive memory (ReRAM) to further enhance the performance and energy efficiency. Specifically, we employ the general principles behind processing-in-memory to design efficient ReRAM based accelerators that support both testing and training operations. Related circuit and architecture optimization will be discussed too. 

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4. Investigation of ReRAM Variability on Flow-Based Edge Detection Computing Using HfO ₂ -Based ReRAM Arrays

   https://doi.org/10.1109/TCSI.2021.3072210  

   Rafiq, Sarah; Hazra, Jubin; Liehr, Maximilian; Beckmann, Karsten; Abedin, Minhaz; Pannu, Jodh S.; Jha, Sumit K.; Cady, Nathaniel C. (July 2021, IEEE Transactions on Circuits and Systems I: Regular Papers)
5. SRA: a secure ReRAM-based DNN accelerator

   https://doi.org/10.1145/3489517.3530440  

   Zhao, Lei; Zhang, Youtao; Yang, Jun (July 2022, Proceedings of the 59th ACM/IEEE Design Automation Conference)