GaN high-electron-mobility transistors (HEMTs) are known to have no avalanche capability and insufficient short-circuit robustness. Recently, breakthrough avalanche and short-circuit capabilities have been experimentally demonstrated in a vertical GaN fin-channel junction-gate field-effect transistor (Fin-JFET), which shows a good promise for using GaN devices in automotive powertrains and electric grids. In particular, GaN Fin-JFETs demonstrated good short-circuit capability at avalanche breakdown voltage (BV AVA ), with a failure-to-open-circuit (FTO) signature. This work presents a comprehensive device physics-based study of the GaN Fin-JFET under short-circuit conditions, particularly at a bus voltage close to BV AVA . Mixed-mode electrothermal TCAD simulations were performed to understand the carrier dynamics, electric field distributions, and temperature profiles in the Fin-JFET under short-circuit and avalanche conditions. The results provide important physical references to understand the unique robustness of the vertical GaN Fin-JFET under the concurrence of short-circuit and avalanche as well as its desirable FTO signature.
Exceptional Repetitive-Short-Circuit Robustness of Vertical GaN Fin-JFET at High Voltage
The limited short circuit (SC) capability of GaN high-electron-mobility transistors (HEMTs) has become a critical concern for their adoption in many power applications. Recently, breakthrough SC robustness was demonstrated in a 650-V rated vertical GaN Fin-JFET with a short circuit withstanding time of over 30 µs at 400 V bus voltage (V BUS ), showing great potential for automotive powertrain and grid applications. This work presents the first study on the repetitive SC robustness of this GaN Fin-JFET at a V BUS of 400 V and 600 V. The GaN Fin-JFET survived 30,000 cycles of 400 V, 10 µs SC stresses without any degradation in device characteristics. At a 600 V V BUS , it survived over 8,000 cycles of 10 µs SC stresses before an open-circuit failure. This open-circuit failure signature allows the GaN Fin-JFET to retain its avalanche breakdown voltage and is highly desirable for system safety. Besides, an increase in gate leakage was observed during the 600 V repetitive test, which can be used as a precursor to predict device failure. As far as we know, this is the first report of an exceptional repetitive SC robustness in a power transistor at a V BUS close to more »
- Award ID(s):
- 2045001
- Publication Date:
- NSF-PAR ID:
- 10396733
- Journal Name:
- Exceptional Repetitive-Short-Circuit Robustness of Vertical GaN Fin-JFET at High Voltage
- Page Range or eLocation-ID:
- 205 to 208
- Sponsoring Org:
- National Science Foundation
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Accepted Manuscript1.0
- Publisher's Version of Record
- https://doi.org/10.1109/ISPSD49238.2022.9813618
