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1. TDMR Detection System with Local Area Influence Probabilistic a Priori Detector

   https://doi.org/10.1109/ICC.2019.8761903  

   Shen, Jinlu; Sun, Xueliang; Sivakumar, Krishnamoorthy; Belzer, Benjamin J.; Chan, Kheong Sann; James, Ashish (July 2019, ICC 2019 - 2019 IEEE International Conference on Communications (ICC))

   We propose a three-track detection system for two dimensional magnetic recording (TDMR) in which a local area influence probabilistic (LAIP) detector works with a trellis-based Bahl-Cocke-Jelinek-Raviv (BCJR) detector to remove intersymbol interference (ISI) and intertrack interference (ITI) among coded data bits as well as media noise due to magnetic grain-bit interactions. Two minimum mean-squared error (MMSE) linear equalizers with different response targets are employed before the LAIP and BCJR detectors. The LAIP detector considers local grain-bit interactions and passes coded bit log-likelihood ratios (LLRs) to the channel decoder, whose output LLRs serve as a priori information to the BCJR detector, which is followed by a second channel decoding pass. Simulation results under 1-shot decoding on a grain-flipping-probability (GFP) media model show that the proposed LAIP/BCJR detection system achieves density gains of 10.16% for center-track detection and 3.13% for three-track detection compared to a standard BCJR/1D-PDNP. The proposed system's BCJR detector bit error rates (BERs) are lower than those of a recently proposed two-track BCJR/2D-PDNP system by factors of (0.55, 0.08) for tracks 1 and 2 respectively. 

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2. Deep Neural Network Based Media Noise Predictors for Use in High-Density Magnetic Recording Turbo-Detectors

   Sayyafan, Amirhossen; Belzer, Benjamin J; Sivakjumar, Krishnamoorthy; Shen, Jinlu; Chan, Kheong Sann; James, Ashish (July 2019, 2019 Magnetic Recording Conference (TMRC 2019))

   Trellis based detection with pattern dependent noise prediction (PDNP) has become standard practice in the HDD industry. In a typical single-track signal processing scheme, the received samples from the read head are first filtered by a linear equalizer with a 1D partial response (PR). The linear filter output flows into a trellis-based (e.g. BCJR) detector that employs a super-trellis based on the PR mask ISI channel and a 1D pattern dependent noise prediction (1D PDNP) algorithm. The effective channel model has a media noise term which models signal dependent noise due to, e.g., magnetic grains intersected by bit boundaries. The media noise can influence two or more bit readback values. The trellis detector sends soft estimates of the coded bits to a channel decoder, which outputs estimates of the user information bits. There are two problems with traditional PDNP. First, when the number of tracks Nt simultaneously processed is greater than one, e.g. in two-dimensional magnetic recording (TDMR), the number of trellis states can become impractically large; this is the state explosion problem. Second, the relatively simple autoregressive noise model and linear prediction used in PDNP is somewhat restrictive and may not accurately represent the media noise, especially at high storage densities; this is the modeling problem. To address the state explosion problem, we separate the ISI detection and media noise prediction into two separate detectors and use the turbo-principle to exchange information between them, thus avoiding use of a super-trellis. To address the modeling problem, we design and train deep neural network (DNN) based media noise predictors. As DNN models are much more general than autoregressive models, they give a more accurate model of magnetic media noise than PDNP; this more accurate modeling results in reduced detector BERs compared to PDNP. 

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3. Towards quantum belief propagation for LDPC decoding in wireless networks

   https://doi.org/10.1145/3372224.3419207  

   Kasi, Srikar; Jamieson, Kyle (September 2020, Proceedings of the 26th Annual International Conference on Mobile Computing and Networking (ACM MobiCom))

   We present Quantum Belief Propagation (QBP), a Quantum Annealing (QA) based decoder design for Low Density Parity Check (LDPC) error control codes, which have found many useful applications in Wi-Fi, satellite communications, mobile cellular systems, and data storage systems. QBP reduces the LDPC decoding to a discrete optimization problem, then embeds that reduced design onto quantum annealing hardware. QBP's embedding design can support LDPC codes of block length up to 420 bits on real state-of-the-art QA hardware with 2,048 qubits. We evaluate performance on real quantum annealer hardware, performing sensitivity analyses on a variety of parameter settings. Our design achieves a bit error rate of 10--8 in 20 μs and a 1,500 byte frame error rate of 10--6 in 50 μs at SNR 9 dB over a Gaussian noise wireless channel. Further experiments measure performance over real-world wireless channels, requiring 30 μs to achieve a 1,500 byte 99.99% frame delivery rate at SNR 15-20 dB. QBP achieves a performance improvement over an FPGA based soft belief propagation LDPC decoder, by reaching a bit error rate of 10--8 and a frame error rate of 10--6 at an SNR 2.5--3.5 dB lower. In terms of limitations, QBP currently cannot realize practical protocol-sized (e.g., Wi-Fi, WiMax) LDPC codes on current QA processors. Our further studies in this work present future cost, throughput, and QA hardware trend considerations. 

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4. Nanopore decoding with speed and versatility for data storage

   https://doi.org/10.1093/bioinformatics/btaf006  

   Volkel, Kevin D; Hook, Paul W; Keung, Albert; Timp, Winston; Tuck, James M (December 2024, Bioinformatics)

   Mathelier, Anthony (Ed.)

   Abstract MotivationAs nanopore technology reaches ever higher throughput and accuracy, it becomes an increasingly viable candidate for reading out DNA data storage. Nanopore sequencing offers considerable flexibility by allowing long reads, real-time signal analysis, and the ability to read both DNA and RNA. We need flexible and efficient designs that match nanopore’s capabilities, but relatively few designs have been explored and many have significant inefficiency in read density, error rate, or compute time. To address these problems, we designed a new single-read per-strand decoder that achieves low byte error rates, offers high throughput, scales to long reads, and works well for both DNA and RNA molecules. We achieve these results through a novel soft decoding algorithm that can be effectively parallelized on a GPU. Our faster decoder allows us to study a wider range of system designs. ResultsWe demonstrate our approach on HEDGES, a state-of-the-art DNA-constrained convolutional code. We implement one hard decoder that runs serially and two soft decoders that run on GPUs. Our evaluation for each decoder is applied to the same population of nanopore reads collected from a synthesized library of strands. These same strands are synthesized with a T7 promoter to enable RNA transcription and decoding. Our results show that the hard decoder has a byte error rate over 25%, while the prior state of the art soft decoder can achieve error rates of 2.25%. However, that design also suffers a low throughput of 183 s/read. Our new Alignment Matrix Trellis soft decoder improves throughput by 257× with the trade-off of a higher byte error rate of 3.52% compared to the state of the art. Furthermore, we use the faster speed of our algorithm to explore more design options. We show that read densities of 0.33 bits/base can be achieved, which is 4× larger than prior MSA-based decoders. We also compare RNA to DNA, and find that RNA has 85% as many error-free reads when compared to DNA. Availability and implementationSource code for our soft decoder and data used to generate figures is available publicly in the Github repository https://github.com/dna-storage/hedges-soft-decoder (10.5281/zenodo.11454877). All raw FAST5/FASTQ data are available at 10.5281/zenodo.11985454 and 10.5281/zenodo.12014515. 

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5. Multi-Stream LDPC Decoder on GPU of Mobile Devices

   https://doi.org/10.1109/CCWC.2019.8666615  

   Amiri, Roohollah; Mehrpouyan, Hani (January 2019, 2019 IEEE 9th Annual Computing and Communication Workshop and Conference (CCWC))

   Low-density parity check (LDPC) codes have been extensively applied in mobile communication systems due to their excellent error correcting capabilities. However, their broad adoption has been hindered by the high complexity of the LDPC decoder. Although to date, dedicated hardware has been used to implement low latency LDPC decoders, recent advancements in the architecture of mobile processors have made it possible to develop software solutions. In this paper, we propose a multi-stream LDPC decoder designed for a mobile device. The proposed decoder uses graphics processing unit (GPU) of a mobile device to achieve efficient real-time decoding. The proposed solution is implemented on an NVIDIA Tegra board as a system on a chip (SoC), where our results indicate that we can control the load on the central processing units through the multi-stream structure. 

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