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1. Boosting Entropy and Enhancing Reliability for Physically Unclonable Functions

   Valles-Novo, Ricardo; Martinez-Sanchez, Andres; Che, Wenjie (December 2020, IEEE Asian Hardware Oriented Security and Trust Symposium)

   null (Ed.)

   Physically Unclonable Functions (PUFs) are emerging hardware security primitives that leverage random variations during chip manufacturing process to generate unique secrets. The security level of generated PUF secrets is mainly determined by its unpredictability feature which is typically evaluated using the metric of entropy bits. In this paper, we propose a novel Pairwise Distinct-Modulus (PDM) technique that significantly improves the upper bound of PUF entropy bits from the scale of log2(N!) up to O(N^2). The PDM technique boosts entropy by eliminating the correlation within PUF response bits caused by element reuse in conventional pairwise comparison. We also propose a reliability-enhancing scheme to compensate the impact on reducing reliability by saving a significant portion of potential reliable response bits. Experimental results based on a published large-scale RO PUF frequency dataset validated that the proposed technique significantly boosts PUF entropy bits from the scale of O(N∙log2(N)) up to approach the new upper bound of O(N^2) with a comparable reliability, and the reliability-enhancing technique saves 4x more on the percentage of reliable response bits. 

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2. Cloud FPGA Security with RO-Based Primitives

   Tian, Shanquan; Krzywosz, Andrew; Giechaskiel, Ilias; Szefer, Jakub (December 2020, International Conference on Field-Programmable Technology (FPT))

   null (Ed.)

   Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are common primitives that can increase the security of user logic on FPGAs. They are typically constructed using Ring Oscillators (ROs). However, PUF and TRNG primitives are not currently available on Cloud FPGAs as some commercial Cloud FPGA providers prohibit deploying ROs implemented using Lookup Tables (LUTs). To aid in bringing RO-based PUFs and TRNGs to commercial Cloud FPGAs, this work implements and evaluates PUFs and TRNGs built using ROs that incorporate latches and flip-flops. The primitives are tested on Amazon's commercial F1 Cloud FPGAs. The designs are the first constructive uses of ROs in Cloud FPGAs and are available under an open-source license. 

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3. Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits

   https://doi.org/10.1145/3517042  

   Cook, Hayden; Arscott, Jacob; George, Brent; Gaskin, Tanner; Goeders, Jeffrey; Hutchings, Brad (December 2022, ACM Transactions on Reconfigurable Technology and Systems)

   This work demonstrates a novel method of accelerating FPGA aging by configuring FPGAs to implement thousands of short circuits, resulting in high on-chip currents and temperatures. Patterns of ring oscillators are placed across the chip and are used to characterize the operating frequency of the FPGA fabric. Over the course of several months of running the short circuits on two-thirds of the reconfigurable fabric, with daily characterization of the FPGA 6 performance, we demonstrate a decrease in FPGA frequency of 8.5%. We demonstrate that this aging is induced in a non-uniform manner. The maximum slowdown outside of the shorted regions is 2.1%, or about a fourth of the maximum slowdown that is experienced inside the shorted region. In addition, we demonstrate that the slowdown is linear after the first two weeks of the experiment and is unaffected by a recovery period. Additional experiments involving short circuits are also performed to demonstrate the results of our initial experiments are repeatable. These experiments also use a more fine-grained characterization method that provides further insight into the non-uniformed nature of the aging caused by short circuits. 

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4. A Novel FPGA-Based Circuit Simulator for Accelerating Reinforcement Learning-Based Design of Power Converters

   https://doi.org/10.1109/ASAP57973.2023.00013  

   Xu, Zhenyu; Yu, Miaoxiang; Yang, Qing Yang; Jeong, Yeonho; Cai, Jillian; Wei, Tao (July 2023, 34th IEEE International Conference on Application-specific Systems, Architectures and Processors.)

   Abstract: High-efficiency energy conversion systems have become increasingly important due to their wide use in all electronic systems such as data centers, smart mobile devices, E-vehicles, medical instruments, and so forth. Complex and interdependent parameters make optimal designs of power converters challenging to get. Recent research has shown that machine learning (ML) algorithms, such as reinforcement learning (RL), show great promise in design of such converter circuits. A trained RL agent can search for optimal design parameters for power conversion circuit topologies under targeted application requirements. Training an RL agent requires numerous circuit simulations. It requires significantly more training iterations when the tolerance of circuit components due to manufacturing inconsistency, aging, and temperature variation is considered. As a result, they may take days to complete, primarily because of the slow time-domain circuit simulation. This paper proposes a new FPGA architecture that accelerates the circuit simulation and hence substantially speeds up the RL-based design method for power converters. Our new architecture supports all power electronic circuit converters and their variations. It substantially improves the training speed of RL-based design methods. High-level synthesis (HLS) was used to build the accelerator on Amazon Web Service (AWS) F1 instance. An AWS virtual PC hosts the training algorithm. The host interacts with the FPGA accelerator by updating the circuit parameters, initiating simulation, and collecting the simulation results during training iterations. A script was created on the host side to facilitate this design method to convert a netlist containing circuit topology and parameters into core matrices in the FPGA accelerator. Experimental results showed 60× overall speedup of our RL-based design method in comparison with using a popular commercial simulator, PowerSim. 

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5. Dynamic Reliability Management in Neuromorphic Computing

   https://doi.org/10.1145/3462330  

   Song, Shihao; Hanamshet, Jui; Balaji, Adarsha; Das, Anup; Krichmar, Jeffrey L.; Dutt, Nikil D.; Kandasamy, Nagarajan; Catthoor, Francky (July 2021, ACM Journal on Emerging Technologies in Computing Systems)

   Neuromorphic computing systems execute machine learning tasks designed with spiking neural networks. These systems are embracing non-volatile memory to implement high-density and low-energy synaptic storage. Elevated voltages and currents needed to operate non-volatile memories cause aging of CMOS-based transistors in each neuron and synapse circuit in the hardware, drifting the transistor’s parameters from their nominal values. If these circuits are used continuously for too long, the parameter drifts cannot be reversed, resulting in permanent degradation of circuit performance over time, eventually leading to hardware faults. Aggressive device scaling increases power density and temperature, which further accelerates the aging, challenging the reliable operation of neuromorphic systems. Existing reliability-oriented techniques periodically de-stress all neuron and synapse circuits in the hardware at fixed intervals, assuming worst-case operating conditions, without actually tracking their aging at run-time. To de-stress these circuits, normal operation must be interrupted, which introduces latency in spike generation and propagation, impacting the inter-spike interval and hence, performance (e.g., accuracy). We observe that in contrast to long-term aging, which permanently damages the hardware, short-term aging in scaled CMOS transistors is mostly due to bias temperature instability. The latter is heavily workload-dependent and, more importantly, partially reversible. We propose a new architectural technique to mitigate the aging-related reliability problems in neuromorphic systems by designing an intelligent run-time manager (NCRTM), which dynamically de-stresses neuron and synapse circuits in response to the short-term aging in their CMOS transistors during the execution of machine learning workloads, with the objective of meeting a reliability target. NCRTM de-stresses these circuits only when it is absolutely necessary to do so, otherwise reducing the performance impact by scheduling de-stress operations off the critical path. We evaluate NCRTM with state-of-the-art machine learning workloads on a neuromorphic hardware. Our results demonstrate that NCRTM significantly improves the reliability of neuromorphic hardware, with marginal impact on performance. 

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