Metal‐semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field‐effect transistors, capable of dynamically altering the operation mode between n‐ or p‐type even during run‐time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al‐Si‐Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top‐gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on‐currents as well as threshold voltages for n‐ and p‐type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of logic gates such as inverters and combinational wired‐AND gates are reported. In this respect, exploiting the advantages of the proposed multi‐gate transistor architecture and offering additional logical inputs, the device functionality can be expanded by transforming a single transistor into a logic gate. Importantly, the demonstrated Al‐Si material system and thereof shown logic gates show high compatibility with state‐of‐the‐art complementary metal‐oxide semiconductor technology. Additionally, exploiting reconfiguration at the device level, this platform may pave the way for future adaptive computing systems with low‐power consumption and reduced footprint, enabling novel circuit paradigms.
This content will become publicly available on June 28, 2024
Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe 2 Thin Film Transistors
Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal–oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on–off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.
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- NSF-PAR ID:
- 10426818
- Date Published:
- Journal Name:
- ACS Nano
- ISSN:
- 1936-0851
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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