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1. EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications

   Emmert, John Martin ; VanDewerker, Sara A. ( July 2021 , 64th IEEE International Midwest Symposium on Circuits and Systems)

   null (Ed.)

   A Muller C-Element is a digital circuit component used in most asynchronous circuits and systems. In Null Convention Logic, the Muller C-Elements make up the subset of THmn threshold gates where the threshold, m, and the input bit- width, n, are equal. This paper presents a new Efficient Muller C- Element implementation, EMC, that is especially suitable for Null Convention Logic applications with high input bit-widths, and it is much faster and smaller than standard implementations. It has a two-transistor switching delay that is independent of the input bit- width, n, and exhibits low noise and static power consumption. It is suitable for all Muller C-Element applications, especially those like Null Convention Logic register feedback circuits that can have large input bit-widths. To reduce static power consumption, it uses active resistors that are only turned “ON” when necessary. Two output stages are presented to implement the required Muller C- Element digital hysteresis: standard, semi-static cross-coupled inverter version, and differential sense-amplifier option. For large values of n, our circuit requires approximately one-half fewer transistors than combining smaller Null Convention Logic THmn semi-static threshold gates. We have successfully simulated up to n = 1024 at a 65 nm node. 

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2. Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

   https://doi.org/10.1002/aelm.202200567  

   Böckle, Raphael ; Sistani, Masiar ; Bažíková, Martina ; Wind, Lukas ; Sadre‐Momtaz, Zahra ; den_Hertog, Martien_I ; Murphey, Corban_G_E ; Cahoon, James_F ; Weber, Walter_M ( August 2022 , Advanced Electronic Materials)

   Metal‐semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field‐effect transistors, capable of dynamically altering the operation mode between n‐ or p‐type even during run‐time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al‐Si‐Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top‐gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on‐currents as well as threshold voltages for n‐ and p‐type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of logic gates such as inverters and combinational wired‐AND gates are reported. In this respect, exploiting the advantages of the proposed multi‐gate transistor architecture and offering additional logical inputs, the device functionality can be expanded by transforming a single transistor into a logic gate. Importantly, the demonstrated Al‐Si material system and thereof shown logic gates show high compatibility with state‐of‐the‐art complementary metal‐oxide semiconductor technology. Additionally, exploiting reconfiguration at the device level, this platform may pave the way for future adaptive computing systems with low‐power consumption and reduced footprint, enabling novel circuit paradigms.

    

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3. Compact Modeling and Design of Magneto-Electric Transistor Devices and Circuits

   https://doi.org/10.1109/SOCC.2018.8618494  

   Sharma, N. ; Binek, C. ; Marshall, A. ; Bird, J. P. ; Dowben, P. A. ; Nikonov, D. ( January 2019 , 2018 31st IEEE International System-on-Chip Conference (SOCC))

   A Verilog-A based model for the magneto-electric field effect transistor (MEFET) device is implemented and a variety of logic functions based on this device are proposed. These models are used to capture energy consumption and delay per switching event and to benchmark the MEFET with respect to CMOS. Single-source MEFET devices can be used for conventional logic gates like NAND, NOR, inverter and buffer and more complex circuits like the full adder. The dual source MEFET is an enhanced version of the MEFET device which functions like a spin multiplexer (spin-MUXer). Circuits using MEFETs require fewer components than CMOS to generate the same logic operation. These devices display a high on-off ratio., unlike many magneto-electric devices., and they operate at very low voltages., resulting in lower switching energy. Benchmarking results show that these devices perform better in terms of energy and delay., for implementing more complex functions., than the basic logic gates. 

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4. Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration

   Miketic, Ivan ; Salman, Emre ( September 2020 , IEEE International System-on-Chip Conference (SOCC))

   Charge-recycling adiabatic circuits are recently receiving increased attention due to both high energy-efficiency and higher resistance against side-channel attacks. These characteristics make adiabatic circuits a promising technique for Internet-of-things based applications. One of the important limitations of adiabatic logic is the higher intra-cell interconnect capacitance due to differential outputs and cross-coupled pMOS transistors. Since energy consumption has quadratic dependence on capacitance in adiabatic circuits (unlike conventional static CMOS where dependence is linear), higher interconnect capacitance significantly degrades the overall power savings that can be achieved by adiabatic logic, particularly in nanoscale technologies. In this paper, monolithic 3D integrated adiabatic circuits are introduced where transistor-level monolithic 3D technology is used to implement adiabatic gates. A 45 nm two-tier Mono3D PDK is used to demonstrate the proposed approach. Monolithic inter-tier vias are leveraged to significantly reduce parasitic interconnect capacitance, achieving up to 47% reduction in power-delay product as compared to 2D adiabatic circuits in a 45 nm technology node. 

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5. Dual‐Mode Organic Electrochemical Transistors Based on Self‐Doped Conjugated Polyelectrolytes for Reconfigurable Electronics

   https://doi.org/10.1002/adma.202200274  

   Nguyen‐Dang, Tung ; Chae, Sangmin ; Chatsirisupachai, Jirat ; Wakidi, Hiba ; Promarak, Vinich ; Visell, Yon ; Nguyen, Thuc‐Quyen ( April 2022 , Advanced Materials)

   Reconfigurable organic logic devices are promising candidates for next generations of efficient computing systems and adaptive electronics. Ideally, such devices would be of simple structure and design, be power efficient, and compatible with high‐throughput microfabrication techniques. This work reports an organic reconfigurable logic gate based on novel dual‐mode organic electrochemical transistors (OECTs), which employ a self‐doped conjugated polyelectrolyte as the active material, which then allows the transistors to operate in both depletion mode and enhancement mode. Furthermore, mode switching is accomplished by simply altering the polarity of the applied gate and drain voltages, which can be done on the fly. In contrast, achieving similar mode‐switching functionality with other organic transistors typically requires complex molecular design or multi‐device engineering. It in shown that dual‐mode functionality is enabled by the concurrent existence of anion doping and cation dedoping of the films. A device physics model that accurately describes the behavior of these transistors is developed. Finally, the utility of these dual‐mode transistors for implementing reconfigurable logic by fabricating a logic gate that may be switched between logic gates AND to NOR, and OR to NAND on the fly is demonstrated.

    

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