This content will become publicly available on July 17, 2024
- Award ID(s):
- 1806285
- NSF-PAR ID:
- 10439196
- Date Published:
- Journal Name:
- Applied Physics Letters
- Volume:
- 123
- Issue:
- 3
- ISSN:
- 0003-6951
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Room-temperature, pulsed-operation lasing of 8.5 μm-emitting InP-based quantum cascade lasers (QCLs), with low threshold-current density and watt-level output power, is demonstrated from structures grown on (001) GaAs substrates by metal-organic chemical vapor deposition. Prior to growing the laser structure, which contains a 35-stage In 0.53 Ga 0.47 As/In 0.52 Al 0.48 As lattice-matched active-core region, a ∼2 μm-thick nearly fully relaxed InP buffer with strained 1.6 nm-thick InAs quantum-dot-like dislocation-filter layers was grown. A smooth terminal buffer-layer surface, with roughness as low as 0.4 nm on a 10 × 10 μm 2 scale, was obtained, while the estimated threading-dislocation density was in the mid-range × 10 8 cm −2 . A series of measurements, on lasers grown on InP metamorphic buffer layers (MBLs) and on native InP substrates, were performed for understanding the impact of the buffer-layer's surface roughness, residual strain, and threading-dislocation density on unipolar devices such as QCLs. As-cleaved devices, grown on InP MBLs, were fabricated as 25 μm × 3 mm deep-etched ridge guides with lateral current injection. The results are pulsed maximum output power of 1.95 W/facet and a low threshold-current density of 1.86 kA/cm 2 at 293 K. These values are comparable to those obtained from devices grown on InP: 2.09 W/facet and 2.42 kA/cm 2 . This demonstrates the relative insensitivity of the device-performance metrics on high residual threading-dislocation density, and high-performance InP-based QCLs emitting near 8 μm can be achieved on lattice-mismatched substrates.more » « less
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Tunneling field effect transistors (TFETs) have gained much interest in the previous decade for use in low power CMOS electronics due to their sub-thermal switching [1]. To date, all TFETs are fabricated as vertical nanowires or fins with long, difficult processes resulting in long learning cycle and incompatibility with modern CMOS processing. Because most TFETs are heterojunction TFETs (HJ-TFETs), the geometry of the device is inherently vertically because dictated by the orientation of the tunneling HJ, achieved by typical epitaxy. Template assisted selective epitaxy was demonstrated for vertical nanowires [2] and horizontally arranged nanorods [3] for III-V on Si integration. In this work, we report results on the area selective and template assisted epitaxial growth of InP, utilizing SiO2 based confined structures on InP substrates, which enables horizontal HJs, that can find application in the next generation of TFET devices. The geometries of the confined structures used are so that only a small area of the InP substrate, dubbed seed, is visible to the growth atmosphere. Growth is initiated selectively only at the seed and then proceeds in the hollow channel towards the source hole. As a result, growth resembles epitaxial lateral overgrowth from a single nucleation point [4], reaping the benefits of defect confinement and, contrary to spontaneous nanowire growth, allows orientation in an arbitrary, template defined direction. Indium phosphide 2-inch (110) wafers are used as the starting substrate. The process flow (Fig.1) consists of two plasma enhanced chemical vapor deposition (PECVD) steps of SiO2, appropriately patterned with electron beam lithography (EBL), around a PECVD amorphous silicon sacrificial layer. The sacrificial layer is ultimately wet etched with XeF2 to form the final, channel like template. Not shown in the schematic in Fig.1 is an additional, ALD deposited, 3 nm thick, alumina layer which prevents plasma damage to the starting substrate and is removed via a final tetramethylammonium hydroxide (TMAH) based wet etch. As-processed wafers were then diced and loaded in a Thomas Swan Horizontal reactor. Successful growth conditions found were 600°C with 4E6 mol/min of group III precursor, a V/III ratio of 400 and 8 lpm of hydrogen as carrier gas. Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) were used as In and P precursors respectively. Top view SEM (Fig.2) confirms growth in the template thanks to sufficient Z-contrast despite the top oxide layer, not removed before imaging. TEM imaging shows a cross section of the confined structure taken at the seed hole (Fig.3). The initial growth interface suggests growth was initiated at the seed hole and atomic order of the InP conforms to the SiO2 template both at the seed and at the growth front. A sharp vertical facet is an encouraging result for the future development of vertical HJ based III-V semiconductor devices.more » « less
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