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Abstract Atomically thin, 2D, and semiconducting transition metal dichalcogenides (TMDs) are seen as potential candidates for complementary metal oxide semiconductor (CMOS) technology in future nodes. While high‐performance field effect transistors (FETs), logic gates, and integrated circuits (ICs) made from n‐type TMDs such as MoS2and WS2grown at wafer scale have been demonstrated, realizing CMOS electronics necessitates integration of large area p‐type semiconductors. Furthermore, the physical separation of memory and logic is a bottleneck of the existing CMOS technology and must be overcome to reduce the energy burden for computation. In this article, the existing limitations are overcome and for the first time, a heterogeneous integration of large area grown n‐type MoS2and p‐type vanadium doped WSe2FETs with non‐volatile and analog memory storage capabilities to achieve a non–von Neumann 2D CMOS platform is introduced. This manufacturing process flow allows for precise positioning of n‐type and p‐type FETs, which is critical for any IC development. Inverters and a simplified 2‐input‐1‐output multiplexers and neuromorphic computing primitives such as Gaussian, sigmoid, and tanh activation functions using this non–von Neumann 2D CMOS platform are also demonstrated. This demonstration shows the feasibility of heterogeneous integration of wafer scale 2D materials.
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Metal‐Guided Selective Growth of 2D Materials: Demonstration of a Bottom‐Up CMOS Inverter
Abstract 2D transition metal dichalcogenide (TMD) layered materials are promising for future electronic and optoelectronic applications. The realization of large‐area electronics and circuits strongly relies on wafer‐scale, selective growth of quality 2D TMDs. Here, a scalable method, namely, metal‐guided selective growth (MGSG), is reported. The success of control over the transition‐metal‐precursor vapor pressure, the first concurrent growth of two dissimilar monolayer TMDs, is demonstrated in conjunction with lateral or vertical TMD heterojunctions at precisely desired locations over the entire wafer in a single chemical vapor deposition (VCD) process. Owing to the location selectivity, MGSG allows the growth of p‐ and n‐type TMDs with spatial homogeneity and uniform electrical performance for circuit applications. As a demonstration, the first bottom‐up complementary metal‐oxide‐semiconductor inverter based on p‐type WSe2and n‐type MoSe2is achieved, which exhibits a high and reproducible voltage gain of 23 with little dependence on position.
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- Award ID(s):
- 1719875
- PAR ID:
- 10461640
- Publisher / Repository:
- Wiley Blackwell (John Wiley & Sons)
- Date Published:
- Journal Name:
- Advanced Materials
- Volume:
- 31
- Issue:
- 18
- ISSN:
- 0935-9648
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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