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1. Internal-Distributed CDM ESD Protection

   https://doi.org/10.1109/EDTM50988.2021.9421054  

   Di, Mengfu; Pan, Zijin; Li, Cheng; Wang, Albert (January 2021, Proc. IEEE Electron Devices Technology and Manufacturing Conference (EDTM))

   CDM ESD protection is a major ESD protection design challenge for advanced ICs, often suffering from random design failures. It was recently reported that the traditional pad-based CDM ESD protection method is fundamentally faulty, contributing to design uncertainties in CDM ESD testing and field failures. This paper reports a novel internally distributed CDM ESD protection method to overcome this major design challenge, which was validated using an internal-CDM-protected oscillator IC implemented in a foundry 45nm SOI CMOS technology. ESD protection is required for all systems. 

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2. Analysis Of CPU Loading Effect On ESD Susceptibility

   https://doi.org/10.1109/EMCSI38923.2020.9191545  

   Izadi, Omid Hoseini; Shumiya, Hideki; Konno, Shota; Araki, Kenji; Pommerenke, David; Kim, DongHyun (July 2020, 2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI))

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3. ESD Protection Designs: Topical Overview and Perspective

   Cheng Li, Zijin Pan (July 2022, Nanomaterials)

   Abstract: As the ever increasing demands for performance of integrated circuit (IC) chip continue to increase, while technology scaling driven by Moore’s Law is becoming extremely challenging if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based CMOS chips. The underlying basis for using HI tech-nologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control and actua-tion, which are required to facilitate comprehensive human-world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within ac-ceptable design constraints including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits and system architectures, making it practically impossible to provide one single compre-hensive review of everything in the field in one paper. This article chooses to offer a topical over-view of selected HI structures that have been validated in CMOS platform, including a stacked-via vertical magnetic-cored inductor structure in CMOS, a metal wall structure in the backend of line (BEOL) of CMOS to suppress global flying noises, an above-IC graphene NEMS switch and a nano crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects 

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4. ESD Protection Designs: Topical Overview and Perspective

   https://doi.org/10.1109/TDMR.2022.3178420  

   Pan, Zijin; Li, Cheng; Hao, Weiquan; Li, Xunyu; Wang, Albert (September 2022, IEEE Transactions on Device and Materials Reliability)
5. Transient Analysis of ESD Protection Circuits for High-Speed ICs

   https://doi.org/10.1109/TEMC.2021.3071644  

   Meiguni, Javad; Zhou, Jianchi; Maghlakelidze, Giorgi; Xu, Yang; Hoseini Izadi, Omid; Marathe, Shubhankar; Shen, Li; Bub, Sergej; Holland, Steffen; Beetner, Daryl; et al (October 2021, IEEE Transactions on Electromagnetic Compatibility)