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Abstract Metal‐semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field‐effect transistors, capable of dynamically altering the operation mode between n‐ or p‐type even during run‐time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al‐Si‐Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top‐gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on‐currents as well as threshold voltages for n‐ and p‐type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of logic gates such as inverters and combinational wired‐AND gates are reported. In this respect, exploiting the advantages of the proposed multi‐gate transistor architecture and offering additional logical inputs, the device functionality can be expanded by transforming a single transistor into a logic gate. Importantly, the demonstrated Al‐Si material system and thereof shown logic gates show high compatibility with state‐of‐the‐art complementary metal‐oxide semiconductor technology. Additionally, exploiting reconfiguration at the device level, this platform may pave the way for future adaptive computing systems with low‐power consumption and reduced footprint, enabling novel circuit paradigms.
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Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi‐Wire Channels
Abstract In this work, bottom‐up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top‐down fabricated nanosheet (NS) and multi‐wire (MW) reconfigurable field‐effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on‐ and off‐currents as well as threshold voltages for n‐ and p‐type operation exhibit a high degree of symmetry. Most notably also a low device‐to‐device variability is achieved. In this respect, the investigated Al–Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired‐AND gate obtained from a multi‐gate RFET. Additionally, up‐scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al–Si–Al platform has substantial potential to enable complex adaptive and self‐learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits.
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- Award ID(s):
- 2121643
- PAR ID:
- 10479005
- Publisher / Repository:
- Wiley Blackwell (John Wiley & Sons)
- Date Published:
- Journal Name:
- Advanced Electronic Materials
- Volume:
- 10
- Issue:
- 2
- ISSN:
- 2199-160X
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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