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1. High-Frequency Tellurene MOSFETs with Biased Contacts

   https://doi.org/10.1109/IMS19712.2021.9574853  

   Xiong, Kuanchen; Qiu, Gang; Wang, Yixiu; Li, Lei; Goritz, Alexander; Lisker, Marco; Wietstruck, Matthias; Kaynak, Mehmet; Wu, Wenzhuo; Ye, Peide D.; et al (June 2021, 2021 IEEE MTT-S International Microwave Symposium (IMS))
2. Device-level Transient Cooling of β-Ga2O3 MOSFETs

   https://doi.org/10.1109/iTherm54085.2022.9899595  

   Kim, Samuel H.; Spencer Lundh, James; Shoemaker, Daniel; Chatterjee, Bikramjit; Chabak, Kelson D.; Green, Andrew J.; Liddy, Kyle; Graham, Samuel; Choi, Sukwon (September 2022, Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM))

   In this study, we compared the transient self-heating behavior of a homoepitaxial β-Ga2O3 MOSFET and a GaN-on-Si HEMT using nanoparticle-assisted Raman thermometry and thermoreflectance thermal imaging. The effectiveness of bottom-side and double-side cooling schemes using a polycrystalline diamond substrate and a diamond passivation layer were studied via transient thermal modeling. Because of the low thermal diffusivity of β-Ga2O3, the use of a β-Ga2O3 composite substrate (bottom-side cooling) must be augmented by a diamond passivation layer (top-side cooling) to effectively cool the device active region under both steady-state and transient operating conditions. Without no proper cooling applied, the steady-state device-to-package thermal resistance of a homoepitaxial β-Ga2O3 MOSFET is 2.6 times higher than that for a GaN-on-Si HEMT. Replacing the substrate with polycrystalline diamond (under a 6.5 μm-thick β-Ga2O3 layer) could reduce the steady-state temperature rise by 65% compared to that for a homoepitaxial β-Ga2O3 MOSFET. However, for high frequency power switching applications beyond the ~102 kHz range, bottom-side cooling (integration with a high thermal conductivity substrate) does not improve the transient thermal response of the device. Adding a diamond passivation over layer diamond not only suppresses the steadystate temperature rise, but also drastically reduces the transient temperature rise under high frequency operating conditions. 

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3. Electro-Thermal Investigation of GaN Vertical Trench MOSFETs

   https://doi.org/10.1109/LED.2021.3065362  

   Chatterjee, Bikramjit; Ji, Dong; Agarwal, Anchal; Chan, Silvia H.; Chowdhury, Srabanti; Choi, Sukwon (May 2021, IEEE Electron Device Letters)
4. Ultra-Wide Band Gap Ga2O3-on-SiC MOSFETs

   https://doi.org/10.1021/acsami.2c21048  

   Song, Yiwen; Bhattacharyya, Arkka; Karim, Anwarul; Shoemaker, Daniel; Huang, Hsien-Lien; Roy, Saurav; McGray, Craig; Leach, Jacob H.; Hwang, Jinwoo; Krishnamoorthy, Sriram; et al (January 2023, ACS Applied Materials & Interfaces)

   Ultra-wide band gap semiconductor devices based on β-phase gallium oxide (Ga2O3) offer the potential to achieve higher switching performance and efficiency and lower manufacturing cost than that of today’s wide band gap power electronics. However, the most critical challenge to the commercialization of Ga2O3 electronics is overheating, which impacts the device performance and reliability. We fabricated a Ga2O3/4H–SiC composite wafer using a fusion-bonding method. A low-temperature (≤600 °C) epitaxy and device processing scheme was developed to fabricate MOSFETs on the composite wafer. The low-temperature-grown epitaxial Ga2O3 devices deliver high thermal performance (56% reduction in channel temperature) and a power figure of merit of (∼300 MW/cm2), which is the highest among heterogeneously integrated Ga2O3 devices reported to date. Simulations calibrated based on thermal characterization results of the Ga2O3-on-SiC MOSFET reveal that a Ga2O3/diamond composite wafer with a reduced Ga2O3 thickness (∼1 μm) and a thinner bonding interlayer (<10 nm) can reduce the device thermal impedance to a level lower than that of today’s GaN-on-SiC power switches. 

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5. Temperature-Dependent Characteristics and Electrostatic Threshold Voltage Tuning of Accumulated Body MOSFETs

   https://doi.org/10.1109/TED.2022.3184906  

   Talukder, A. B.; Smith, Brittany; Akbulut, Mustafa; Dirisaglik, Faruk; Silva, Helena; Gokirmak, Ali (June 2022, IEEE Transactions on Electron Devices)

   Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing ( Vside ). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage ( Vt ) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm × 78 nm (width × length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and Vt increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. Vt can be adjusted from ∼ 0.3 to ∼ 1.1 V with ∼ 0.3 V/V sensitivity by depletion or accumulation of the body of the device using Vside . This high level of tunability allows electronic control of Vt and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents ( < 10 −13 A). 

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