Low InP/dielectric interface trap density Dit will enable low subthreshold swings (SS) in mm-wave MOSFETs [1] using InGaAs/InP composite channels [2] for increased breakdown and in tunnel FETs (TFETs) [3] using InAs/InP heterojunctions [4] for increased tunneling probability. Reducing Dit at the etched InP mesa edges of DHBTs and avalanche photodiodes will reduce leakage currents and increase breakdown voltages. While it can be difficult [5] to extract Dit of III-V interfaces from MOSCAP characteristics, Dit can be readily determined from the SS of long gate length Lg MOSFETs. Here we report InP-channel MOSFETs with record low SS indicating record low Dit at the semiconductor-dielectric interface. The devices use a AlOxNy/ZrO2 gate dielectric and a 14nm channel thickness Tch. A sample of 13 MOSFETs at 2 m Lg shows SS=70mV/dec. (mean) ±3 mV/dec. (standard deviation), corresponding to a minimum Dit ~3×1012 cm-2eV-1. The lowest SS observed at 2 m Lg is 66 mV/dec. The results suggest that wide-bandgap InP layers can be incorporated into MOS device designs without large degradations in DC characteristics arising from interface defects
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Temperature-Dependent Characteristics and Electrostatic Threshold Voltage Tuning of Accumulated Body MOSFETs
Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing ( Vside ). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage ( Vt ) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm × 78 nm (width × length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and Vt increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. Vt can be adjusted from ∼ 0.3 to ∼ 1.1 V with ∼ 0.3 V/V sensitivity by depletion or accumulation of the body of the device using Vside . This high level of tunability allows electronic control of Vt and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents ( < 10 −13 A).
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- Award ID(s):
- 1711626
- PAR ID:
- 10342040
- Date Published:
- Journal Name:
- IEEE Transactions on Electron Devices
- ISSN:
- 0018-9383
- Page Range / eLocation ID:
- 1 to 6
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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