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1. Efficient Hardware Implementation of Finite Field Arithmetic AB+C for Binary Ring-LWE Based Post-Quantum Cryptography

   https://doi.org/10.1109/TETC.2021.3091982  

   Xie, Jiafeng; He, Pengzhou; Wang, Xiaofang Maggie; Imana, Jose Luis (April 2022, IEEE Transactions on Emerging Topics in Computing)

   Post-quantum cryptography (PQC) has gained significant attention from the community recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from the well-developed quantum computers. The finite field arithmetic AB+C , where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper, we propose a novel hardware implementation of the finite field arithmetic AB+C through three stages of interdependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware architecture is then presented with detailed description; (iii) a thorough implementation has also been given along with the comparison. Overall, (i) the proposed basic structure ( u=1 ) outperforms the existing designs, e.g., it involves 55.9% less area-delay product (ADP) than [13] for n=512 ; (ii) the proposed design also offers very efficient performance in time-complexity and can be used in many future applications. 

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2. Approximate Quantum Array Multiplier

   https://doi.org/10.1109/QCE60285.2024.00017  

   Crimmins, Aden; Lopez_Alarcon, Sonia (September 2024, IEEE)

   Multiplication is a frequent computation in many algorithms, classical and quantum. This paper targets the implementation of quantum integer multiplication. Quantum array multipliers take inspiration from classical array multipliers, with the result of reduced circuit depth. They take advantage of the quantum phase domain, through rotations controlled by the multiplier’s qubits. This work further explores this implementation by applying approximate rotations. Although this approach can have an impact on the accuracy of the result, the reduction in depth can result in better outcomes when noise is involved. 

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3. Parallel Verification for delta-Equivalence of Neural Network Quantization

   https://doi.org/10.1007/978-3-031-65112-0_4  

   Huang, Pei; Yang, Yuting; Wu, Haoze; Daukantas, Ieva; Wu, Min; Jia, Fuqi; Barrett, Clark (January 2024, Springer Nature Switzerland)

   Avni, Guy; Giacobbe, Mirco; Johnson, Taylor T; Katz, Guy; Lukina, Anna; Narodytska, Nina; Schilling, Christian (Ed.)

   Quantization replaces floating point arithmetic with integer arithmetic in deep neural networks, enabling more efficient on-device inference with less power and memory. However, it also brings in loss of generalization and even potential errors to the models. In this work, we propose a parallelization technique for formally verifying the equivalence between quantized models and their original real-valued counterparts. In order to guarantee both soundness and completeness, mixed integer linear programming (MILP) is deployed as the baseline technique. Nevertheless, the incorporation of two networks as well as the mixture of integer and real number arithmetic make the problem much more challenging than verifying a single network, and thus using MILP alone is inadequate for the non-trivial cases. To tackle this, we design a distributed verification technique that can leverage hundreds of CPUs on high-performance computing clusters. We develop a two-tier parallel framework and propose property- and output-based partition strategies. Evaluated on perception networks quantized with PyTorch, our approach outperforms existing methods in successfully verifying many cases that are otherwise considered infeasible. 

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4. Towards Verifying Nonlinear Integer Arithmetic

   Beame, Paul; Liew, Vincent (August 2018, arXiv.org)

   We eliminate a key roadblock to efficient verification of nonlinear integer arithmetic using CDCL SAT solvers, by showing how to construct short resolution proofs for many properties of the most widely used multiplier circuits. Such short proofs were conjectured not to exist. More precisely, we give n^{O(1)} size regular resolution proofs for arbitrary degree 2 identities on array, diagonal, and Booth multipliers and n^{O(log n)} size proofs for these identities on Wallace tree multipliers. 

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5. Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber

   https://doi.org/10.1109/ISCAS48785.2022.9937606  

   Tu, Yazheng; He, Pengzhou; Lee, Chiou-Yng; Chasaki, Danai; Xie, Jiafeng (May 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS))

   Recent advances in quantum computing have initiated a new round of cryptosystem innovation as the existing public-key cryptosystems are proven to be vulnerable to quantum attacks. Several types of cryptographic algorithms have been proposed for possible post-quantum cryptography (PQC) candidates and the lattice-based key encapsulation mechanism (KEM) Saber is one of the most promising algorithms. Noticing that the polynomial multiplication over ring is the key arithmetic operation of KEM Saber, in this paper, we propose a novel strategy for efficient implementation of polynomial multiplication on the hardware platform. First of all, we present the proposed mathematical derivation process for polynomial multiplication. Then, the proposed hardware structure is provided. Finally, field-programmable gate array (FPGA) based implementation results are obtained, and it is shown that the proposed design has better performance than the existing ones. The proposed polynomial multiplication can be further deployed to construct efficient hardware cryptoprocessors for KEM Saber. 

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