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1. A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC

   Sravan Pulipati, Viduneth Ariyarathna (November 2019, 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS))

   null (Ed.)

   This paper discusses early results associated with a fully-digital direct-conversion array receiver at 28 GHz. The proposed receiver makes use of commercial off-the-shelf (COTS) electronics, including the receiver chain. The design consists of a custom 28 GHz patch antenna sub-array providing gain in the elevation plane, with azimuthal plane beamforming provided by real-time digital signal processing (DSP) algorithms running on a Xilinx Radio Frequency System on Chip (RF SoC). The proposed array receiver employs element-wise fully-digital array processing that supports ADC sample rates up to 2 GS/second and up to 1 GHz of operating bandwidth per antenna. The RF mixed-signal data conversion circuits and DSP algorithms operate on a single-chip RFSoC solution installed on the Xilinx ZCU1275 prototyping platform. 

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2. Resolution-Adaptive All-Digital Spatial Equalization for mmWave Massive MU-MIMO

   https://doi.org/10.1109/SPAWC51858.2021.9593110  

   Castaneda, Oscar; Mirfarshbafan, Seyed Hadi; Ghajari, Shahaboddin; Molnar, Alyosha; Jacobsson, Sven; Durisi, Giuseppe; Studer, Christoph (September 2021, IEEE 22nd International Workshop on Signal Processing Advances in Wireless Communications (SPAWC))

   All-digital basestation (BS) architectures for millimeter-wave (mmWave) massive multi-user multiple-input multiple-output (MU-MIMO), which equip each radio-frequency chain with dedicated data converters, have advantages in spectral efficiency, flexibility, and baseband-processing simplicity over hybrid analog-digital solutions. For all-digital architectures to be competitive with hybrid solutions in terms of power consumption, novel signal-processing methods and baseband architectures are necessary. In this paper, we demonstrate that adapting the resolution of the analog-to-digital converters (ADCs) and spatial equalizer of an all-digital system to the communication scenario (e.g., the number of users, modulation scheme, and propagation conditions) enables orders-of-magnitude power savings for realistic mmWave channels. For example, for a 256-BS-antenna 16-user system supporting 1 GHz bandwidth, a traditional baseline architecture designed for a 64-user worst-case scenario would consume 23 W in 28 nm CMOS for the ADC array and the spatial equalizer, whereas a resolution-adaptive architecture is able to reduce the power consumption by 6.7×. 

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3. Variational Bayes for Joint Channel Estimation and Data Detection in Few-Bit Massive MIMO Systems

   https://doi.org/10.1109/TSP.2024.3429009  

   Nguyen, Ly V; Swindlehurst, A Lee; Nguyen, Duy_H N (July 2024, IEEE Transactions on Signal Processing)

   Massive multiple-input multiple-output (MIMO) communications using low-resolution analog-to-digital converters (ADCs) is a promising technology for providing high spectral and energy efficiency with affordable hardware cost and power consumption. However, the use of low-resolution ADCs requires special signal processing methods for channel estimation and data detection since the resulting system is severely non-linear. This paper proposes joint channel estimation and data detection methods for massive MIMO systems with low-resolution ADCs based on the variational Bayes (VB) inference framework. We first derive matched-filter quantized VB (MF-QVB) and linear minimum mean-squared error quantized VB (LMMSE-QVB) detection methods assuming the channel state information (CSI) is available. Then we extend these methods to the joint channel estimation and data detection (JED) problem and propose two methods we refer to as MF-QVB-JED and LMMSE-QVB-JED. Unlike conventional VB-based detection methods that assume knowledge of the second-order statistics of the additive noise, we propose to float the elements of the noise covariance matrix as unknown random variables that are used to account for both the noise and the residual inter-user interference. We also present practical aspects of the QVB framework to improve its implementation stability. Finally, we show via numerical results that the proposed VB-based methods provide robust performance and also significantly outperform existing methods. 

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4. A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

   https://doi.org/10.3390/electronics10050590  

   Tasneem, Nishat Tarannum; Mahbub, Ifana (March 2021, Electronics)

   This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system. 

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5. Design of a Reverse-Electrowetting Transducer Based Wireless Self-powered Motion Sensor

   https://doi.org/10.1109/ISCAS45731.2020.9180973  

   Tasneem, Nishat T.; Biswas, Dipon K.; Adhikari, Pashupati R.; Reid, Russell; Mahbub, Ifana (October 2020, IEEE International Symposium on Circuits and Systems proceedings)

   This paper presents a self-powered motion sensor based on reverse-electrowetting on dielectric (REWOD) energy harvesting having the capability of remotely keeping a track of any motion activity. The energy harvester includes a rectifier and a voltage regulator to provide the DC supply voltage to the analog front-end and the transmitter to wirelessly transfer the data from the motion sensor. The on-chip circuitry includes a seven-stage voltage-doubler based rectifier, an amplifier, an analog-to-digital converter (ADC), and a transmitter, and is designed in standard 180 nm CMOS process with a supply voltage of 1.8 V. The recycled folded cascode (RFC) based charge amplifier has a closed-loop gain of 53 dB within the bandwidth of 1-150 Hz, which is suitable to detect any low-frequency motion signal. An 8-bit SAR-ADC is designed to digitize the amplified signal with a sampling rate of 1 ksamples/s. The transmitter used for this application operates in the 3.1-5 GHz frequency band with an energy efficiency of 8.5 pJ/pulse at 100 kbps data rate. The wireless motion sensing device with the REWOD can be suitable for quantitatively monitoring the motion-related data as a wearable sensor. 

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