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Abstract Ferroelectric tunneling junctions (FTJs) with tunable tunneling electroresistance (TER) are promising for many emerging applications, including non-volatile memories and neurosynaptic computing. One of the key challenges in FTJs is the balance between the polarization value and the tunneling current. In order to achieve a sizable on-current, the thickness of the ferroelectric layer needs to be scaled down below 5 nm. However, the polarization in these ultra-thin ferroelectric layers is very small, which leads to a low tunneling electroresistance (TER) ratio. In this paper, we propose and demonstrate a new type of FTJ based on metal/Al2O3/Zr-doped HfO2/Si structure. The interfacial Al2O3layer and silicon substrate enable sizable TERs even when the thickness of Zr-doped HfO2(HZO) is above 10 nm. We found that F-N tunneling dominates at read voltages and that the polarization switching in HZO can alter the effective tunneling barrier height and tune the tunneling resistance. The FTJ synapses based on Al2O3/HZO stacks show symmetric potentiation/depression characteristics and widely tunable conductance. We also show that spike-timing-dependent plasticity (STDP) can be harnessed from HZO based FTJs. These novel FTJs will have high potential in non-volatile memories and neural network applications.
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Implementation of high-performance and high-yield nanoscale hafnium zirconium oxide based ferroelectric tunnel junction devices on 300 mm wafer platform
In this work, hafnium zirconium oxide (HZO)-based 100 × 100 nm2 ferroelectric tunnel junction (FTJ) devices were implemented on a 300 mm wafer platform, using a baseline 65 nm CMOS process technology. FTJs consisting of TiN/HZO/TiN were integrated in between metal 1 (M1) and via 1 (V1) layers. Cross-sectional transmission electron microscopy and energy dispersive x-ray spectroscopy analysis confirmed the targeted thickness and composition of the FTJ film stack, while grazing incidence, in-plane x-ray diffraction analysis demonstrated the presence of orthorhombic phase Pca21 responsible for ferroelectric polarization observed in HZO films. Current measurement, as a function of voltage for both up- and down-polarization states, yielded a tunneling electroresistance (TER) ratio of 2.28. The device TER ratio and endurance behavior were further optimized by insertion of thin Al2O3 tunnel barrier layer between the bottom electrode (TiN) and ferroelectric switching layer (HZO) by tuning the band offset between HZO and TiN, facilitating on-state tunneling conduction and creating an additional barrier layer in off-state current conduction path. Investigation of current transport mechanism showed that the current in these FTJ devices is dominated by direct tunneling at low electric field (E < 0.4 MV/cm) and by Fowler–Nordheim (F–N) tunneling at high electric field (E > 0.4 MV/cm). The modified FTJ device stack (TiN/Al2O3/HZO/TiN) demonstrated an enhanced TER ratio of ∼5 (2.2× improvement) and endurance up to 106 switching cycles. Write voltage and pulse width dependent trade-off characteristics between TER ratio and maximum endurance cycles (Nc) were established that enabled optimal balance of FTJ switching metrics. The FTJ memory cells also showed multi-level-cell characteristics, i.e., 2 bits/cell storage capability. Based on full 300 mm wafer statistics, a switching yield of >80% was achieved for fabricated FTJ devices demonstrating robustness of fabrication and programming approach used for FTJ performance optimization. The realization of CMOS-compatible nanoscale FTJ devices on 300 mm wafer platform demonstrates the promising potential of high-volume large-scale industrial implementation of FTJ devices for various nonvolatile memory applications.
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- Award ID(s):
- 2123863
- PAR ID:
- 10524782
- Publisher / Repository:
- American Vacuum Society
- Date Published:
- Journal Name:
- Journal of Vacuum Science & Technology B
- Volume:
- 41
- Issue:
- 1
- ISSN:
- 2166-2746
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Abstract Hf 0.5 Zr 0.5 O 2 (HZO) thin films are promising candidates for non-volatile memory and other related applications due to their demonstrated ferroelectricity at the nanoscale and compatibility with Si processing. However, one reason that HZO has not been fully scaled into industrial applications is due to its deleterious wake-up and fatigue behavior which leads to an inconsistent remanent polarization during cycling. In this study, we explore an interfacial engineering strategy in which we insert 1 nm Al 2 O 3 interlayers at either the top or bottom HZO/TiN interface of sequentially deposited metal-ferroelectric-metal capacitors. By inserting an interfacial layer while limiting exposure to the ambient environment, we successfully introduce a protective passivating layer of Al 2 O 3 that provides excess oxygen to mitigate vacancy formation at the interface. We report that TiN/HZO/TiN capacitors with a 1 nm Al 2 O 3 at the top interface demonstrate a higher remanent polarization (2P r ∼ 42 μ C cm −2 ) and endurance limit beyond 10 8 cycles at a cycling field amplitude of 3.5 MV cm −1 . We use time-of-flight secondary ion mass spectrometry, energy dispersive spectroscopy, and grazing incidence x-ray diffraction to elucidate the origin of enhanced endurance and leakage properties in capacitors with an inserted 1 nm Al 2 O 3 layer. We demonstrate that the use of Al 2 O 3 as a passivating dielectric, coupled with sequential ALD fabrication, is an effective means of interfacial engineering and enhances the performance of ferroelectric HZO devices.more » « less
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Ferroelectric hafnium-zirconium oxide (HZO) is an excellent candidate for low-power non-volatile memory applications due to its demonstrated ferroelectricity at the nanoscale and compatibility with silicon-based technologies. The interface of HZO in contact with its electrode, typically TiN in a metal–ferroelectric–metal (MFM) capacitor configuration, is of particular interest because factors, such as volume confinement, impurity concentration, interfacial layers, thermal expansion mismatch, and defect trapping, are believed to play a crucial role in the ferroelectric performance of HZO-based devices. Processing variables, such as precursor type, oxygen source, dose duration, and deposition temperature, are known to strongly affect the quality of the oxide–metal interface. However, not many studies have focused on the effect of breaking or maintaining vacuum during MFM deposition. In this study, sequential, no-atmosphere processing (SNAP) is employed to avoid atmospheric exposure, where electrode TiN and ferroelectric HZO are deposited sequentially in the atomic layer deposition chamber without breaking vacuum. The effect of breaking vacuum during the sequential deposition steps is elucidated by fabricating and characterizing MFM capacitors with and without intentional vacuum breaks prior to the deposition of the HZO and top TiN. Using x-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry (ToF-SIMS), we reveal that breaking vacuum after bottom TiN electrode deposition leads to interfacial oxidation and increased carbon contamination, which preferentially stabilizes the non-ferroelectric tetragonal phase and lead to diminished remanent polarization. Avoiding carbon impurities and interfacial TiOx at the HZO and TiN interface using SNAP leads to heightened remanent polarization, reduced leakage current density, and elimination of the wake-up effect. Our work highlights the effect of vacuum breaking on the processing-structure-properties of HZO-based capacitors, revealing that maintaining vacuum can significantly improve ferroelectric properties.more » « less
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This study investigates the electrical characteristics observed in n-channel and p-channel ferroelectric field effect transistor (FeFET) devices fabricated through a similar process flow with 10 nm of ferroelectric hafnium zirconium oxide (HZO) as the gate dielectric. The n-FeFETs demonstrate a faster complete polarization switching compared to the p-channel counterparts. Detailed and systematic investigations using TCAD simulations reveal the role of fixed charges and interface traps at the HZO-interfacial layer (HZO/IL) interface in modulating the subthreshold characteristics of the devices. A characteristic crossover point observed in the transfer characteristics of n-channel devices is attributed with the temporary switching between ferroelectric-based operation to charge-based operation, caused by the pinning effect due to the presence of different traps. This experimental study helps understand the role of charge trapping effects in switching characteristics of n- and p-channel ferroelectric FETs.more » « less
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Ferroelectric tunnel junctions (FTJs) based on epitaxial complex oxide heterostructures are promising building blocks for developing low power nanoelectronics and neuromorphic computing. FTJs consisting of correlated oxide electrodes have distinct advantages in size scaling but only yield moderate electroresistance (ER) at room temperature due to the challenge in imposing asymmetric interfacial screening and large modulation of the tunneling potential profile. Here, we achieve large ER in all-oxide FTJs by paring a correlated metal with a narrow bandgap Mott insulator as electrodes. We fabricate epitaxial FTJs composed of 2.8 and 4 nm PbZr0.2Ti0.8O3 tunnel barriers sandwiched between correlated oxides LaNiO3 and Sr3Ir2O7 electrodes. An ER of 6500% has been observed at room temperature, which increases to over 105% at 100 K. The high ER can be attributed to ferroelectric polarization induced metal–insulator transition in interfacial Sr3Ir2O7, which enhances the potential asymmetry for the tunnel barrier. The temperature dependence of tunneling current shows that direct tunneling dominates in the on state, while the off-state conduction transitions from thermally activated behavior at high temperatures to Glazman–Matveev defect-mediated inelastic tunneling at low temperatures. Our study provides a viable material strategy for designing all-oxide FTJs with high ER, facilitating their implementation in nonvolatile memories and energy-efficient computing devices.more » « less
- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1116/6.0002097
