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Multi-channel data acquisition of bio-signals is a promising technology that is being used in many fields these days. Compressed sensing (CS) is an innovative approach of signal processing that facilitates sub-Nyquist processing of bio-signals, such as an electrocardiogram (ECG) and electroencephalogram (EEG). This strategy can be used to lower the data rate to realize ultra-low-power performance, As the count of recording channels increase, data volume is increased resulting in impermissible transmitting power. This paper presents the implementation of a CMOS-based front-end design with the CS in the standard 180 nm CMOS process. A novel pseudo-random sequence generator is proposed, which consists of two different types of D flip-flops that are used for obtaining a completely random sequence. The power consumed by the bio-signal amplifier block is 2.35 μW. The SAR-ADC block that is designed to digitize the amplified signal consumes 277 μW of power and the power consumption value of the pseudo-random bit sequence generator (PRBS) is 344.2μW. The sampling rate of PRBS block is 611.76 Kbps. We have considered collecting neural data from the 32 channels, and achieved an 8.5X compression rate. The low power consumption per channel confirms the importance of the proposed approach for multiple channel high-density neural interfaces.
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Efficient in vivo neural signal compression using an autoencoder-based neural network
Conventional in vivo neural signal processing involves extracting spiking activity within the recorded signals from an ensemble of neurons and transmitting only spike counts over an adequate interval. However, for brain-computer interface (BCI) applications utilizing continuous local field potentials (LFPs) for cognitive decoding, the volume of neural data to be transmitted to a computer imposes relatively high data rate requirements. This is particularly true for BCIs employing high-density intracortical recordings with hundreds or thousands of electrodes. This article introduces the first autoencoder-based compression digital circuit for the efficient transmission of LFP neural signals. Various algorithmic and architectural-level optimizations are implemented to significantly reduce the computational complexity and memory requirements of the designed in vivo compression circuit. This circuit employs an autoencoder-based neural network, providing a robust signal reconstruction. The application-specific integrated circuit (ASIC) of the in vivo compression logic occupies the smallest silicon area and consumes the lowest power among the reported state-of-the-art compression ASICs. Additionally, it offers a higher compression rate and a superior signal-to-noise and distortion ratio.
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- Award ID(s):
- 2007131
- PAR ID:
- 10528765
- Publisher / Repository:
- IEEE Transactions on Biomedical Circuits and Systems
- Date Published:
- Journal Name:
- IEEE transactions on biomedical circuits and systems
- ISSN:
- 1932-4545
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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