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1. Thermal optimization of two-terminal SOT-MRAM

   https://doi.org/10.1063/5.0211620  

   Su, Haotian; Kwon, Heungdong; Hwang, William; Xue, Fen; Köroğlu, Çağıl; Tsai, Wilman; Asheghi, Mehdi; Goodson, Kenneth E; Wang, Shan X; Pop, Eric (July 2024, Journal of Applied Physics)

   While magnetoresistive random-access memory (MRAM) stands out as a leading candidate for embedded nonvolatile memory and last-level cache applications, its endurance is compromised by substantial self-heating due to the high programming current density. The effect of self-heating on the endurance of the magnetic tunnel junction (MTJ) has primarily been studied in spin-transfer torque (STT)-MRAM. Here, we analyze the transient temperature response of two-terminal spin–orbit torque (SOT)-MRAM with a 1 ns switching current pulse using electro-thermal simulations. We estimate a peak temperature range of 350–450 °C in 40 nm diameter MTJs, underscoring the critical need for thermal management to improve endurance. We suggest several thermal engineering strategies to reduce the peak temperature by up to 120 °C in such devices, which could improve their endurance by at least a factor of 1000× at 0.75 V operating voltage. These results suggest that two-terminal SOT-MRAM could significantly outperform conventional STT-MRAM in terms of endurance, substantially benefiting from thermal engineering. These insights are pivotal for thermal optimization strategies in the development of MRAM technologies. 

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2. GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM

   Angizi, Shaahin; Sun, Jiao; Zhang, Wei; Fan, Deliang (March 2019, 23rd Design Automation and Test in Europe)

   In this work, we present GraphS architecture, which transforms current Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) to massively parallel computational units capable of accelerating graph processing applications. GraphS can be leveraged to greatly reduce energy consumption dealing with underlying adjacency matrix computations, eliminating unnecessary off-chip accesses and providing ultra-high internal bandwidth. The device-to-architecture co-simulation for three social network data-sets indicate roughly 3.6X higher energy efficiency and 5.3X speed-up over recent ReRAM crossbar. It achieves ~4X higher energy-efficiency and 5.1X speed-up over recent processing-in-DRAM acceleration methods. 

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3. GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM

   https://doi.org/10.23919/DATE.2019.8715270  

   Angizi, Shaahin; Sun, Jiao; Zhang, Wei; Fan, Deliang (March 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE))
4. High-Density STT-Assisted SOT-MRAM (SAS-MRAM) for Energy-Efficient AI Applications

   https://doi.org/10.1109/TMAG.2024.3486616  

   Xue, Fen; Hwang, William; Zhang, Fan; Tsai, Wilman; Fan, Deliang; Wang, Shan X (April 2025, IEEE Transactions on Magnetics)
5. Exploring DNA Alignment-in-Memory Leveraging Emerging SOT-MRAM

   https://doi.org/10.1145/3386263.3407590  

   Angizi, Shaahin; Zhang, Wei; Fan, Deliang (September 2020, Proceedings of the 2020 on Great Lakes Symposium on VLSI)

   null (Ed.)

   In this work, we review two alternative Processing-in-Memory (PIM) accelerators based on Spin-Orbit-Torque Magnetic Random Access Memory (SOT-MRAM) to execute DNA short read alignment based on an optimized and hardware-friendly alignment algorithm. We first discuss the reconstruction of the existing sequence alignment algorithm based on BWT and FM-index such that it can be fully implemented leveraging PIM functions. We then transform SOT-MRAM array to a potential computational memory by presenting two different reconfigurable sense amplifiers to accelerate the reconstructed alignment-in-memory algorithm. The cross-layer simulation results show that such PIM platforms are able to achieve a nearly ten-fold and two-fold increases in throughput/power/area measure compared with recent ASIC and processing-in-ReRAM designs, respectively. 

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