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Approximate computing (AC) leverages the inherent error resilience and is used in many big-data applications from various domains such as multimedia, computer vision, signal processing, and machine learning to improve systems performance and power consumption. Like many other approximate circuits and algorithms, the memory subsystem can also be used to enhance performance and save power significantly. This paper proposes an efficient and effective systematic methodology to construct an approximate non-volatile magneto-resistive RAM (MRAM) framework using consumer-off-the-shelf (COTS) MRAM chips. In the proposed scheme, an extensive experimental characterization of memory errors is performed by manipulating the write latency of MRAM chips which exploits the inherent (intrinsic/extrinsic process variation) stochastic switching behavior of magnetic tunnel junctions (MTJs). The experimental results, involving error-resilient image compression and machine learning applications, reveal that the proposed AC framework provides a significant performance improvement and demonstrates a reduction in MRAM write energy of ~47.5% on average with negligible or no loss in output quality.
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This content will become publicly available on April 1, 2026
High-Density STT-Assisted SOT-MRAM (SAS-MRAM) for Energy-Efficient AI Applications
- Award ID(s):
- 2314591
- PAR ID:
- 10586959
- Publisher / Repository:
- IEEE
- Date Published:
- Journal Name:
- IEEE Transactions on Magnetics
- Volume:
- 61
- Issue:
- 4
- ISSN:
- 0018-9464
- Page Range / eLocation ID:
- 1 to 8
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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