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This paper introduces an on-chip analog calibration method tailored for differential temperature sensors in thermal monitoring applications. A three-step calibration process is proposed within a two-stage high-gain instrumentation amplifier to compensate for the output voltage offset due to device mismatches and on-chip temperature gradients. The calibration circuits were designed in a standard 65 nm CMOS process for simulation. Results indicate that an input-referred offset with a mean of 0.2 μV can be achieved after calibration, through which the standard deviation is greatly reduced from σ = 880.3 μV to σ = 5086 μV. Furthermore, the proposed analog offset calibration scheme has negligible impact on the sensitivity of the complete temperature sensor circuit, as shown by Monte Carlo and process-temperature corner simulation results.
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This content will become publicly available on June 1, 2026
A Low-Power Differential Temperature Sensor with Chopped Cascode Transistors and Switched-Capacitor Integration
Embedded differential temperature sensors can be utilized to monitor the power consumption of circuits, taking advantage of the inherent on-chip electrothermal coupling. Potential applications range from hardware security to linearity, gain/bandwidth calibration, defect-oriented testing, and compensation for circuit aging effects. This paper introduces the use of on-chip differential temperature sensors as part of a wireless Internet of Things system. A new low-power differential temperature sensor circuit with chopped cascode transistors and switched-capacitor integration is described. This design approach leverages chopper stabilization in combination with a switched-capacitor integrator that acts as a low-pass filter such that the circuit provides offset and low-frequency noise mitigation. Simulation results of the proposed differential temperature sensor in a 65 nm complementary metal-oxide-semiconductor (CMOS) process show a sensitivity of 33.18V/°C within a linear range of ±36.5m°C and an integrated output noise of 0.862mVrms (from 1 to 441.7 Hz) with an overall power consumption of 0.187mW. Considering a figure of merit that involves sensitivity, linear range, noise, and power, the new temperature sensor topology demonstrates a significant improvement compared to state-of-the-art differential temperature sensors for on-chip monitoring of power dissipation.
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- PAR ID:
- 10630374
- Publisher / Repository:
- Electronics
- Date Published:
- Journal Name:
- Electronics
- Volume:
- 14
- Issue:
- 12
- ISSN:
- 2079-9292
- Page Range / eLocation ID:
- 2381
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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