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1. (Digital Presentation) Multimodal Encapsulation of p-SnOx to Engineer the Carrier Density for Thin Film Transistor Applications

   https://doi.org/10.1149/MA2022-0215821mtgabs  

   Lee, Dong Hun; Zhang, Yuxuan; No, Kwangsoo; Song, Han Wook; Lee, Sunghwan (October 2022, ECS Meeting Abstracts)

   It has been challenging to synthesize p-type SnO_x(1≤x<2) and engineer the electrical properties such as carrier density and mobility due to the narrow processing window and the localized oxygen 2p orbitals near the valence band. We recently reported on the processing of p-type SnOx and an oxide-based p-n heterostructures, demonstrating high on/off rectification ratio (>10³), small turn-on voltage (<0.5 V), and low saturation current (~1×10^-10A)¹. In order to further understand the p-type oxide and engineer the properties for various electronic device applications, it is important to identify (or establish) the dominating doping and transport mechanisms. The low dopability in p-type SnOx, of which the causation is also closely related to the narrow processing window, needs to be mitigated so that the electrical properties of the material are to be adequately engineered^{2, 3}. Herein, we report on the multifunctional encapsulation of p-SnO_xto limit the surface adsorption of oxygen and selectively permeate hydrogen into the p-SnO_xchannel for thin film transistor (TFT) applications. Time-of-flight secondary ion mass spectrometry measurements identified that ultra-thin SiO₂as a multifunctional encapsulation layer effectively suppressed the oxygen adsorption on the back channel surface of p-SnO_xand augmented hydrogen density across the entire thickness of the channel. Encapsulated p-SnO_x-based TFTs demonstrated much-enhanced channel conductance modulation in response to the gate bias applied, featuring higher on-state current and lower off-state current. The relevance between the TFT performance and the effects of oxygen suppression and hydrogen permeation is discussed in regard to the intrinsic and extrinsic doping mechanisms. These results are supported by density-functional-theory calculations. Acknowledgement This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS. K.N. was supported by Basic Science Research Program (NRF-2021R11A1A01051246) through the NRF Korea funded by the Ministry of Education. ReferencesLee, D. H.; Park, H.; Clevenger, M.; Kim, H.; Kim, C. S.; Liu, M.; Kim, G.; Song, H. W.; No, K.; Kim, S. Y.; Ko, D.-K.; Lucietto, A.; Park, H.; Lee, S., High-Performance Oxide-Based p–n Heterojunctions Integrating p-SnOx and n-InGaZnO.ACS Applied Materials & Interfaces2021,13(46), 55676-55686.Hautier, G.; Miglio, A.; Ceder, G.; Rignanese, G.-M.; Gonze, X., Identification and design principles of low hole effective mass p-type transparent conducting oxides.Nat Commun2013,4.Yim, K.; Youn, Y.; Lee, M.; Yoo, D.; Lee, J.; Cho, S. H.; Han, S., Computational discovery of p-type transparent oxide semiconductors using hydrogen descriptor.npj Computational Materials2018,4(1), 17. Figure 1 

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2. (Invited) Oxide Electronics and Recent Progress in Bipolar Applications

   https://doi.org/10.1149/MA2022-01191071mtgabs  

   Lee, Sunghwan; Lee, Donghun; Qin, Fei; Zhang, Yuxuan; Rothschild, Molly; Song, Han Wook; No, Kwangsoo (July 2022, ECS Meeting Abstracts)

   The discovery of oxide electronics is of increasing importance today as one of the most promising new technologies and manufacturing processes for a variety of electronic and optoelectronic applications such as next-generation displays, batteries, solar cells, memory devices, and photodetectors[1]. The high potential use seen in oxide electronics is due primarily to their high carrier mobilities and their ability to be fabricated at low temperatures[2]. However, since the majority of oxide semiconductors are n-type oxides, current applications are limited to unipolar devices, eventually developing oxide-based bipolar devices such as p-n diodes and complementary metal-oxide semiconductors. We have contributed to a wide range of oxide semiconductors and their electronics and optoelectronic device applications. Particularly, we have demonstrated n-type oxide-based thin film transistors (TFT), integrating In 2 O 3 -based n-type oxide semiconductors from binary cation materials to ternary cation species including InZnO, InGaZnO (IGZO), and InAlZnO. We have suggested channel/metallization contact strategies to achieve stable and high TFT performance[3, 4], identified vacancy-based native defect doping mechanisms[5], suggested interfacial buffer layers to promote charge injection capability[6], and established the role of third cation species on the carrier generation and carrier transport[7]. More recently, we have reported facile manufacturing of p-type SnOx through reactive magnetron sputtering from a Sn metal target[8]. The fabricated p-SnOx was found to be devoid of metallic phase of Sn from x-ray photoelectron spectroscopy and demonstrated stable performance in a fully oxide-based p-n heterojunction together with n-InGaZnO. The oxide-based p-n junctions exhibited a high rectification ratio greater than 10 3 at ±3 V, a low saturation current of ~2x10 -10 , and a small turn-on voltage of -0.5 V. In this presentation, we review recent achievements and still remaining issues in transition metal oxide semiconductors and their device applications, in particular, bipolar applications including p-n heterostructures and complementary metal-oxide-semiconductor devices as well as single polarity devices such as TFTs and memristors. In addition, the fundamental mechanisms of carrier transport behaviors and doping mechanisms that govern the performance of these oxide-based devices will also be discussed. ACKNOWLEDGMENT This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS. K.N. was supported by Basic Science Research Program (NRF-2021R11A1A01051246) through the NRF Korea funded by the Ministry of Education. REFERENCES [1] K. Nomura et al. , Nature, vol. 432, no. 7016, pp. 488-492, Nov 25 2004. [2] D. C. Paine et al. , Thin Solid Films, vol. 516, no. 17, pp. 5894-5898, Jul 1 2008. [3] S. Lee et al. , Journal of Applied Physics, vol. 109, no. 6, p. 063702, Mar 15 2011, Art. no. 063702. [4] S. Lee et al. , Applied Physics Letters, vol. 104, no. 25, p. 252103, 2014. [5] S. Lee et al. , Applied Physics Letters, vol. 102, no. 5, p. 052101, Feb 4 2013, Art. no. 052101. [6] M. Liu et al. , ACS Applied Electronic Materials, vol. 3, no. 6, pp. 2703-2711, 2021/06/22 2021. [7] A. Reed et al. , Journal of Materials Chemistry C, 10.1039/D0TC02655G vol. 8, no. 39, pp. 13798-13810, 2020. [8] D. H. Lee et al. , ACS Applied Materials & Interfaces, vol. 13, no. 46, pp. 55676-55686, 2021/11/24 2021. 

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3. Strategies to Enhance the Capability of Carrier Injection to the Effective Channel for Bottom-gated Amorphous Oxide Thin Films Transistors

   Liu, Mingyuan; Kim, Hyeonghun; Song, Han Wook; Lee, Sunghwan (November 2021, Materials Research Society)

   Over the two decades, amorphous oxide semiconductors (AOSs) and their thin film transistor (TFT) channel application have been intensely explored to realize high performance, transparent and flexible displays due to their high field effect mobility (μFE=5-20 cm2/Vs), visible range optical transparency, and low temperature processability (25-300 °C).[1-2] The metastable amorphous phase is to be maintained during operation by the addition of Zn and additional third cation species (e.g., Ga, Hf, or Al) as an amorphous phase stabilizer.[3-5] To limit TFT off-state currents, a thin channel layer (10-20 nm) was employed for InZnO (IZO)-based TFTs, or third cations were added to suppress carrier generations in the TFT channel. To resolve bias stress-induced instabilities in TFT performance, approaches to employ defect passivation layers or enhance channel/dielectric interfacial compatibility were demonstrated.[6-7] Metallization contact is also a dominating factor that determines the performance of TFTs. Particularly, it has been reported that high electrical contact resistance significantly sacrifices drain bias applied to the channel, which leads to undesirable power loss during TFT operation and issues for the measurement of TFT field effect mobilities. [2, 8] However, only a few reports that suggest strategies to enhance contact behaviors are available in the literature. Furthermore, the previous approaches (1) require an additional fabrication complexity due to the use of additional treatments at relatively harsh conditions such as UV, plasma, or high temperatures, and (2) may lead to adverse effects on the channel material attributed to the chemical incompatibility between dissimilar materials, and exposures to harsh environments. Therefore, a simple and easy but effective buffer strategy, which does not require any additional process complexities and not sacrifice chemical compatibility, needs to be established to mitigate the contact issues and therefore achieve high performance and low power consumption AOS TFTs. The present study aims to demonstrate an approach utilizing an interfacial buffer layer, which is compositionally homogeneous to the channel to better align work functions between channel and metallization without a significant fabrication complexity and harsh treatment conditions. Photoelectron spectroscopic measurements reveal that the conducting IZO buffer, of which the work function (Φ) is 4.37 eV, relaxes a relatively large Φ difference between channel IZO (Φ=4.81 eV) and Ti (Φ=4.2-4.3 eV) metallization. The buffer is found to lower the energy barrier for charge carriers at the source to reach the effective channel region near the dielectric. In addition, the higher carrier density of the buffer and favorable chemical compatibility with the channel (compositionally the same) further contribute to a significant reduction in specific contact resistance as much as more than 2.5 orders of magnitude. The improved contact and carrier supply performance from the source to the channel lead to an enhanced field effect mobility of up to 56.49 cm2/Vs and a threshold voltage of 1.18 V, compared to 13.41 cm2/Vs and 7.44 V of IZO TFTs without a buffer. The present work is unique in that an approach to lower the potential barrier between the source and the effective channel region (located near the channel/dielectric interface, behaving similar to a buried-channel MOSFET [9]) by introducing a contact buffer layer that enhances the field effect mobility and facilitates carrier supply from the source to the effective channel region. 

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4. Mitigating Heavy Ion Irradiation‐Induced Degradation in p‐type SnO Thin‐Film Transistors at Room Temperature

   https://doi.org/10.1002/pssa.202300392  

   Al-Mamun, Nahid Sultan; Rasel, Md Abu Jafar; Wolfe, Douglas E.; Haque, Aman; Schoell, Ryan; Hattar, Khalid; Ryu, Seung Ho; Kim, Seong Keun (September 2023, physica status solidi (a))

   The study investigates the mitigation of radiation damage on p‐type SnO thin‐film transistors (TFTs) with a fast, room‐temperature annealing process. Atomic layer deposition is utilized to fabricate bottom‐gate TFTs of high‐quality p‐type SnO layers. After 2.8 MeV Au⁴⁺irradiation at a fluence level of 5.2 × 10¹² ions cm⁻², the output drain current and on/off current ratio (I_on/I_off) decrease by more than one order of magnitude, field‐effect mobility (μ_FE) reduces more than four times, and subthreshold swing (SS) increases more than four times along with a negative shift in threshold voltage. The observed degradation is attributed to increased surface roughness and defect density, as confirmed by scanning electron microscopy (SEM), high‐resolution micro‐Raman, and transmission electron microscopy (TEM) with geometric phase analysis (GPA). A technique is demonstrated to recover the device performance at room temperature and in less than a minute, using the electron wind force (EWF) obtained from low‐duty‐cycle high‐density pulsed current. At a pulsed current density of 4.0 × 10⁵ A cm⁻², approximately four times increase inI_on/I_offis observed, 41% increase inμ_FE, and 20% decrease in the SS of the irradiated TFTs, suggesting effectiveness of the new annealing technique. 

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5. The effect of intrinsic layer on the performance of oxide-based p-i-n heterojunctions integrating p-SnOx and n-InGaZnO

   Lee, Dong Hun; Lee, Sunghwan (May 2022, Materials Research Society)

   The discovery of oxide electronics is of increasing importance today as one of the most promising new technologies and manufacturing processes for a variety of electronic and optoelectronic applications such as next-generation displays, batteries, solar cells, and photodetectors. The high potential use seen in oxide electronics is due primarily to their high carrier mobilities and their ability to be fabricated at low temperatures. However, since the majority of oxide semiconductors are n-type oxides, current applications are limited to unipolar devices, eventually developing oxide-based bipolar devices such as p-n diodes and complementary metal-oxide semiconductors. We have contributed to wide range of oxide semiconductors and their electronics and optoelectronic device applications. Particularly, we have demonstrated n-type oxide-based thin film transistors (TFT), integrating In2O3-based n-type oxide semiconductors from binary cation materials to ternary cation species including InZnO, InGaZnO (IGZO), and InAlZnO. We have suggested channel/metallization contact strategies to achieve stable TFT performance, identified vacancy-based native defect doping mechanisms, suggested interfacial buffer layers to promote charge injection capability, and established the role of third cation species on the carrier generation and carrier transport. More recently, we have reported facile manufacturing of p-type SnOx through reactive magnetron sputtering from a Sn metal target. The fabricated p-SnOx was found to be devoid of metallic phase of Sn from x-ray photoelectron spectroscopy and demonstrated stable performance in a fully oxide based p-n heterojunction together with n-InGaZnO. The oxide-based p-n junctions exhibited a high rectification ratio greater than 103 at ±3 V, a low saturation current of ~2x10-10, and a small turn-on voltage of -0.5 V. With all the previous achievements and investigations about p-type oxide semiconductors, challenges remain for implementing p-type oxide realization. For the implementation of oxide-based p-n heterojunctions, the performance needs to be further enhanced. The current on/off ration may be limited, in our device structure, due to either high reverse saturation current (or current density) or non-ideal performance. In this study, two rational strategies are suggested to introduce an “intrinsic” layer, which is expected to reduce the reverse saturation current between p-SnOx and n-IGZO and hence increase the on/off ratio. The carrier density of n-IGZO is engineered in-situ during the sputtering process, by which compositionally homogeneous IGZO with significantly reduced carrier density is formed at the interface. Then, higher carrier density IGZO is formed continuously on the lower carrier density IGZO during the sputtering process without any exposure of the sample to the air. Alternatively, heterogeneous oxides of MgO and SiO2 are integrated into between p-SnOx and n-IGZO, by which the defects on the surface can be passivated. The interfacial properties are thoroughly investigated using transmission electron microscopy and atomic force microscopy. The I-V characteristics are compared between the set of devices integrated with two types of “intrinsic” layers. The current research results are expected to contribute to the development of p-type oxides and their industrial application manufacturing process that meets current processing requirements, such as mass production in p-type oxide semiconductors. 

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