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Abstract—Recent advances in process technology have resulted in novel defect mechanisms making the test generation process very challenging. In addition to complete opens and shorts that can be represented via extreme defect resistance magnitudes, partial resistive opens and shorts are also of concern in deeply scaled CMOS technologies. For open defects with intermediate defect magnitude values, it has been shown that multi-pattern tests are necessary for defect exposure. We extend this approach to short defects with intermediate defect magnitude values to obtain a suite of multi-pattern tests for standard cell instances that cover complete as well as partial intra-cell open and short defects. A hierarchical scan-compatible SAT-based test generation approach for full scan sequential circuits is then proposed that allows such multi-pattern tests to be applied to the circuit via the scan infrastructure. A key innovation is the combined use of shift and capture operations along with launch-on-capture and launch-on- shift scan based test application for increased defect coverage. Resulting defect coverage improvements over conventional two-pattern tests are demonstrated on ISCAS89 benchmark circuits.
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This content will become publicly available on September 23, 2026
Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Stringent quality requirements for safety-critical applications drive the demand for “zero defects” in modern ICs. In this context, delay characterization of standard cells for resistive open defects is an increasing concern due to aggressive timing margins in digital circuits. The problem is made worse by the large number of open defect sites in standard cells, combined with a wide range of defect resistance values for each site. This incurs possible prohibitive costs for defect simulation and characterization. To alleviate this complexity, we propose Resistive Fault Dominance (RFD) for resistive open defects. RFD eliminates simulations of certain open defects with intermediate defect resistance values that are guaranteed to exceed specified timing margins for standard cells, based on tests for specific “dominant” open defects. This can significantly reduce the computational costs of cell library characterization and simulation effort by 84%-91%. An algorithmic fault simulation methodology for resistive open defects on parasitic-extracted (PEX) transistor level netlists is developed.
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- Award ID(s):
- 2331002
- PAR ID:
- 10636278
- Publisher / Repository:
- IEEE
- Date Published:
- Edition / Version:
- 1
- Volume:
- 1
- Issue:
- 1
- ISBN:
- 979-8-3315-2014-4
- Page Range / eLocation ID:
- 1-10
- Subject(s) / Keyword(s):
- Open defects Delay fault testing Defect characterization Critical faults Resistive fault dominance Elmore Delay.
- Format(s):
- Medium: X Size: 1MB Other: pdf
- Size(s):
- 1MB
- Location:
- San Diego, CA
- Sponsoring Org:
- National Science Foundation
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