Excessive test power can cause multiple issues at manufacturing as well as during field test. To reduce both shift and capture power during test, we propose a DFT-based approach where we split the scan chains into segments and use extra control bits inserted between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the appropriate values for the control bits in the test patterns. This is true not only for stuck-at fault test sets, but for Launch-off-Capture (LOC) transition tests as well. It eliminates the need for expensive post processing or modification of the ATPG tool. Up to 37% power reduction can be achieved for a stuck-at test set while up to 35% reduction can be achieved for a transition test set for the circuits studied.
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SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Abstract—Recent advances in process technology have resulted
in novel defect mechanisms making the test generation process
very challenging. In addition to complete opens and shorts that
can be represented via extreme defect resistance magnitudes,
partial resistive opens and shorts are also of concern in deeply
scaled CMOS technologies. For open defects with intermediate
defect magnitude values, it has been shown that multi-pattern
tests are necessary for defect exposure. We extend this approach
to short defects with intermediate defect magnitude values to
obtain a suite of multi-pattern tests for standard cell instances
that cover complete as well as partial intra-cell open and short
defects. A hierarchical scan-compatible SAT-based test generation
approach for full scan sequential circuits is then proposed that
allows such multi-pattern tests to be applied to the circuit via the
scan infrastructure. A key innovation is the combined use of shift
and capture operations along with launch-on-capture and launch-on-
shift scan based test application for increased defect coverage.
Resulting defect coverage improvements over conventional two-pattern
tests are demonstrated on ISCAS89 benchmark circuits.
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- Award ID(s):
- 1910964
- NSF-PAR ID:
- 10401353
- Date Published:
- Journal Name:
- 2020 IEEE International Test Conference (ITC)
- Page Range / eLocation ID:
- 1 to 10
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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null (Ed.)Excessive test power can cause multiple issues at manufacturing as well as during field test. To reduce both shift and capture power during test, we propose a DFT-based approach where we split the scan chains into segments and use extra control bits inserted between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the appropriate values for the control bits in the test patterns. This is true not only for stuck-at fault test sets, but for Launch-off-Capture (LOC) transition tests as well. It eliminates the need for expensive post processing or modification of the ATPG tool. Up to 37% power reduction can be achieved for a stuck-at test set while up to 35% reduction can be achieved for a transition test set for the circuits studied.more » « less
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Transition fault testing is an important component of modern testing for delay defects. Unfortunately, test pattern sets for delay defects tend to be significantly longer than test pattern sets for static defects. In the past, various approaches have been devised to detect static defects during scan shift to reduce test time and increase defect coverage. In this paper, we propose a DFT (Design-For-Test) enhancement to allow delay defects to be detected by stuck-at test patterns during scan shift as well.more » « less
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null (Ed.)The use of multicycle tests, with several functional capture cycles between scan operations, contributes significantly to the ability to compact a test set. Multicycle tests have the added benefit that they can contribute to the detection of defects with complex behaviors that are not detected by single-cycle or two-cycle tests. To ensure that this benefit is materialized when test compaction is applied to transition faults, this article suggests to incorporate into the test compaction procedure an additional fault model whose fault coverage increases when multicycle tests are used. To ensure that the computational complexity of test compaction is not increased by a fault model with a large number of faults, or faults with complex behaviors, the added fault model is required to have the same characteristics as the transition fault model. A type of transition fault called unspecified transition fault satisfies these requirements. The article describes a test compaction procedure for transition faults that incorporates unspecified transition faults, and presents experimental results for benchmark circuits to demonstrate the levels of test compaction and fault coverage that can be achieved.more » « less
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null (Ed.)Functional broadside tests were developed to avoid overtesting of delay faults. The tests achieve this goal by creating functional operation conditions during their functional capture cycles. To increase the achievable fault coverage, close-to-functional scan-based tests are allowed to deviate from functional operation conditions. This article suggests that a more comprehensive functional broadside test set can be obtained by replacing target faults that cannot be detected with faults that have similar (but not identical) detection conditions. A more comprehensive functional broadside test set has the advantage that it still maintains functional operation conditions. It covers the test holes created when target faults cannot be detected by detecting similar faults. The article considers the case where the target faults are transition faults. When a standard transition fault, with an extra delay of a single clock cycle, cannot be detected, an unspecified transition fault is used instead. An unspecified transition fault captures the behaviors of transition faults with different extra delays. When this fault cannot be detected, a stuck-at fault is used instead. A stuck-at fault has some of the detection conditions of a transition fault. Multicycle functional broadside tests are used to allow unspecified transition faults to be detected. As a by-product, test compaction also occurs. The structure of the test generation procedure accommodates the complexity of producing functional broadside tests by considering the target as well as replacement faults together. Experimental results for benchmark circuits demonstrate the fault coverage improvements achieved, and the effect on the number of tests.more » « less
- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/ITC44778.2020.9325240
