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Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide–semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS₂field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint. 

The interface properties and thermal stability of bismuth (Bi) contacts on molybdenum disulfide (MoS2) shed light on their behavior under various deposition conditions and temperatures. The examination involves extensive techniques including X-ray photoelectron spectroscopy, scanning tunneling microscopy (STM), and scanning tunneling spectroscopy (STS). Bi contacts formed a van der Waals interface on MoS2 regardless of deposition conditions, such as ultrahigh vacuum (UHV, 3 × 10–11 mbar) and high vacuum (HV, 4 × 10–6 mbar), while the oxidation on MoS2 has been observed. However, the semimetallic properties of Bi suppress the impact of defect states, including oxidized-MoS2 and vacancies. Notably, the n-type characteristic of Bi/MoS2 remains unaffected, and no significant changes in the local density of states near the conduction band minimum are observed despite the presence of defects detected by STM and STS. As a result, the Fermi level (EF) resides below the conduction band of MoS2. The study also examines the impact of annealing on the contact interface, revealing no interface reaction between Bi and MoS2 up to 300 °C. These findings enhance our understanding of semimetal (Bi) contacts on MoS2, with implications for improving the performance and reliability of electronic devices. 

Abstract Two-dimensional (2D) materials have garnered significant attention in recent years due to their atomically thin structure and unique electronic and optoelectronic properties. To harness their full potential for applications in next-generation electronics and photonics, precise control over the dielectric environment surrounding the 2D material is critical. The lack of nucleation sites on 2D surfaces to form thin, uniform dielectric layers often leads to interfacial defects that degrade the device performance, posing a major roadblock in the realization of 2D-based devices. Here, we demonstrate a wafer-scale, low-temperature process (<250 °C) using atomic layer deposition (ALD) for the synthesis of uniform, conformal amorphous boron nitride (aBN) thin films. ALD deposition temperatures between 125 and 250 °C result in stoichiometric films with high oxidative stability, yielding a dielectric strength of 8.2 MV/cm. Utilizing a seed-free ALD approach, we form uniform aBN dielectric layers on 2D surfaces and fabricate multiple quantum well structures of aBN/MoS₂and aBN-encapsulated double-gated monolayer (ML) MoS₂field-effect transistors to evaluate the impact of aBN dielectric environment on MoS₂optoelectronic and electronic properties. Our work in scalable aBN dielectric integration paves a way towards realizing the theoretical performance of 2D materials for next-generation electronics. 

Contact engineering on monolayer layer (ML) semiconducting transition metal dichalcogenides (TMDs) is considered the most challenging problem towards using these materials as a transistor channel in future advanced technology nodes. The typically observed strong Femi level pinning induced in part by the reaction of the source/drain contact metal and the ML TMD frequently results in a large Schottky barrier height, which limits the electrical performance of ML TMD field-effect transistors (FETs). However, at a microscopic level, little is known about how interface defects or reaction sites impact the electrical performance of ML TMD FETs. In this work, we have performed statistically meaningful electrical measurements on at least 120 FETs combined with careful surface analysis to unveil contact resistance dependencies on the interface chemistry. In particular, we achieved a low contact resistance for ML MoS2 FETs with ultra-high vacuum (UHV, 3×10-11 mbar) deposited Ni contacts, ~500 ohm·μm, which is 5 times lower than the contact resistance achieved when deposited at high vacuum (HV, 3×10-6 mbar) conditions. These electrical results strongly correlate with our surface analysis observations. X-ray photoelectron spectroscopy (XPS) revealed significant bonding species between Ni and MoS2 under UHV conditions compared to HV. We also studied the Bi/MoS2 interface under UHV and HV deposition conditions. Different from the case of Ni, we do not observe a difference in contact resistance or interface chemistry between contacts deposited under UHV and HV. Finally, this article also explores the thermal stability and reliability of the two contact metals employed here. 

Abstract Bayesian networks are powerful statistical models to understand causal relationships in real-world probabilistic problems such as diagnosis, forecasting, computer vision, etc. For systems that involve complex causal dependencies among many variables, the complexity of the associated Bayesian networks become computationally intractable. As a result, direct hardware implementation of these networks is one promising approach to reducing power consumption and execution time. However, the few hardware implementations of Bayesian networks presented in literature rely on deterministic CMOS devices that are not efficient in representing the stochastic variables in a Bayesian network that encode the probability of occurrence of the associated event. This work presents an experimental demonstration of a Bayesian network building block implemented with inherently stochastic spintronic devices based on the natural physics of nanomagnets. These devices are based on nanomagnets with perpendicular magnetic anisotropy, initialized to their hard axes by the spin orbit torque from a heavy metal under-layer utilizing the giant spin Hall effect, enabling stochastic behavior. We construct an electrically interconnected network of two stochastic devices and manipulate the correlations between their states by changing connection weights and biases. By mapping given conditional probability tables to the circuit hardware, we demonstrate that any two node Bayesian networks can be implemented by our stochastic network. We then present the stochastic simulation of an example case of a four node Bayesian network using our proposed device, with parameters taken from the experiment. We view this work as a first step towards the large scale hardware implementation of Bayesian networks.