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This paper reports the fabrication of silicon PN diode by using DNA nanostructure as the etching template for SiO₂and also as then-dopant of Si. DNA nanotubes were deposited ontop-type silicon wafer that has a thermal SiO₂layer. The DNA nanotubes catalyze the etching of SiO₂by HF vapor to expose the underlying Si. The phosphate groups in the DNA nanotube were used as the doping source to locallyn-dope the Si wafer to form vertical P-N junctions. Prototype PN diodes were fabricated and exhibited expected blockage behavior with a knee voltage ofca.0.7 V. Our work highlights the potential of DNA nanotechnology in future fabrication of nanoelectronics. 

We place a molecular Bose-Einstein condensate in a 1D shaken lattice with a Floquet-engineered dispersion, and observe the dynamics in both position and momentum space. At the initial condition of zero momentum, our engineered dispersion is inverted, and therefore unstable. We observe that the condensate is destabilized by the lattice shaking as expected, but rather than decaying incoherently or producing jets, as in other unstable condensates, under our conditions the condensate bifurcates into two portions in momentum space, with each portion subsequently following semi-classical trajectories that suffer minimal spreading in momentum space as they evolve. We can model the evolution with a Gross-Pitaevskii equation, which suggests the initial bifurcation is facilitate by a nearly linear “inverted V”-shaped dispersion at the zone center, while the lack of spreading in momentum space is facilitated by interactions, as in a soliton. We propose that this relatively clean bifurcation in momentum space has applications for counter-diabatic preparation of exotic ground states in many-body quantum simulation schemes. 

Optical phase-change materials have enabled nonvolatile programmability in integrated photonic circuits by leveraging a reversible phase transition between amorphous and crystalline states. To control these materials in a scalable manner on-chip, heating the waveguide itself via electrical currents is an attractive option which has been recently explored using various approaches. Here, we compare the heating efficiency, fabrication variability, and endurance of two promising heater designs which can be easily integrated into silicon waveguides—a resistive microheater using n-doped silicon and one using a silicon p-type/intrinsic/n-type (PIN) junction. Raman thermometry is used to characterize the heating efficiencies of these microheaters, showing that both devices can achieve similar peak temperatures but revealing damage in the PIN devices. Subsequent endurance testing and characterization of both device types provide further insights into the reliability and potential damage mechanisms that can arise in electrically programmable phase-change photonic devices. 

Phase change chalcogenides such as Ge₂Sb₂Te₅(GST) have recently enabled advanced optical devices for applications such as in-memory computing, reflective displays, tunable metasurfaces, and reconfigurable photonics. However, designing phase change optical devices with reliable and efficient electrical control is challenging due to the requirements of both high amorphization temperatures and extremely fast quenching rates for reversible switching. Here, we use a Multiphysics simulation framework to model three waveguide-integrated microheaters designed to switch optical phase change materials. We explore the effects of geometry, doping, and electrical pulse parameters to optimize the switching speed and minimize energy consumption in these optical devices. 

To identify superior thermal contacts to graphene, we implement a high-throughput methodology that systematically explores the Ni−Pd alloy composition spectrum and the effect of Cr adhesion layer thickness on thermal interface conductance with monolayer graphene. Frequency domain thermoreflectance measurements of two independently prepared Ni−Pd/Cr/graphene/ SiO2 samples identify a maximum metal/graphene/SiO2 junction thermal interface conductance of 114 ± (39, 25) MW/m2 K and 113 ± (33, 22) MW/m2 K at ∼10 at. % Pd in Ninearly double the highest reported value for pure metals and 3 times that of pure Ni or Pd. The presence of Cr, at any thickness, suppresses this maximum. Although the origin of the peak is unresolved, we find that it correlates with a region of the Ni−Pd phase diagram that exhibits a miscibility gap. Cross-sectional imaging by high-resolution transmission electron microscopy identifies striations in the alloy at this particular composition, consistent with separation into multiple phases. Through this work, we draw attention to alloys in the search for better contacts to two-dimensional materials for next-generation devices. 

To identify superior thermal contacts to graphene we implement a high throughput methodology that systematically explores the Ni-Pd alloy composition spectrum and the effect of Cr adhesion layer thickness on the thermal interface conductance with monolayer CVD graphene. Frequency domain thermoreflectance measurements of two independently prepared Ni- Pd/Cr/graphene/SiO2 samples both identify a maximum in the metal/graphene/SiO2 junction thermal interface conductance of 114± (39, 25) MW/m2K and 113± (33, 22) MW/m2K at ~10 atomic percent Pd in Ni—nearly double the highest reported value for pure metals and three times that of pure Ni or Pd. The presence of Cr, at any thickness, suppresses this maximum. Although the origin of the peak is unresolved, we find that it correlates to a region of the Ni-Pd phase diagram that exhibits a miscibility gap. Cross sectional imaging by high resolution transmission electron microscopy identifies striations in the alloy at this particular composition, consistent with separation into multiple phases. Through this work, we draw attention to alloys in the search for better contacts to 2D materials for next generation devices. 

Neuromorphic computing has recently emerged as a promising paradigm to overcome the von-Neumann bottleneck and enable orders of magnitude improvement in bandwidth and energy efficiency. However, existing complementary metal-oxide-semiconductor (CMOS) digital devices, the building block of our computing system, are fundamentally different from the analog synapses, the building block of the biological neural network—rendering the hardware implementation of the artificial neural networks (ANNs) not scalable in terms of area and power, with existing CMOS devices. In addition, the spatiotemporal dynamic, a crucial component for cognitive functions in the neural network, has been difficult to replicate with CMOS devices. Here, we present the first topological insulator (TI) based electrochemical synapse with programmable spatiotemporal dynamics, where long-term and short-term plasticity in the TI synapse are achieved through the charge transfer doping and ionic gating effects, respectively. We also demonstrate basic neuronal functions such as potentiation/depression and paired-pulse facilitation with high precision (>500 states per device), as well as a linear and symmetric weight update. We envision that the dynamic TI synapse, which shows promising scaling potential in terms of energy and speed, can lead to the hardware acceleration of truly neurorealistic ANNs with superior cognitive capabilities and excellent energy efficiency.