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Electrical Characterization and Benchmarking of Polylithic Integration Using Fused-Silica Stitch-Chips With Compressible Microinterconnects for RF/mm-Wave Applications

https://doi.org/10.1109/TCPMT.2021.3113886

Zheng, Ting; Jo, Paul K.; Rajan, Sreejith Kochupurackal; Bakir, Muhannad S. (November 2021, IEEE Transactions on Components, Packaging and Manufacturing Technology)

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Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs

https://doi.org/10.1109/TCPMT.2020.3011325

Jo, Paul K.; Kochupurackal Rajan, Sreejith; Gonzalez, Joe L.; Bakir, Muhannad S. (September 2020, IEEE Transactions on Components, Packaging and Manufacturing Technology)

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Polylithic Integration for RF/MM-Wave Chiplets using Stitch-Chips: Modeling, Fabrication, and Characterization

https://doi.org/10.1109/IMS30576.2020.9223887

Zheng, T.; Jo, P.; Rajan, S.; Bakir, M. (January 2020, IEEE MTT-S Int. Microw. Symp. (IMS))

A polylithic integration technology is demonstrated for seamless stitching of RF and digital chiplets. In this technology, stitch-chips with compressible microinterconnects (CMIs) are used for low-loss and dense interconnection between chiplets. A testbed using fused-silica stitch-chips with integrated CMIs is demonstrated including modeling, fabrication, assembly, and characterization. A 500 µm-long stitch-chip signal link is measured to have less than 0.4 dB insertion loss up to 30 GHz. A simulated eye diagram for 1000 µm-long stitch-chip signal link has a clear opening at 50 Gbps data rate. Moreover, the S-parameters of the CMIs are extracted from this testbed and show less than 0.17 dB insertion loss up to 30 GHz. Benchmarking to silicon interposer based interconnection is also reported.
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Fiber-Interconnect Silicon Chiplet Technology for Self-Aligned Fiber-to-Chip Assembly

https://doi.org/10.1109/LPT.2019.2923206

Wan, Congshan; Gonzalez, Joe L.; Fan, Tianren; Adibi, Ali; Gaylord, Thomas K.; Bakir, Muhannad S. (August 2019, IEEE Photonics Technology Letters)

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Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching

P. Jo, T. Zhang (January 2019, IEEE Electronic Components and Technology Conf. (ECTC))

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