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1. AC Computing Methodology for RF Powered IoT Security

   Wan, Tutu; Salman, Emre; Stanacevic, Milutin (March 2018, Government Microcircuit Applications & Critical Technology Conference,)

   Hardware security is a critical challenge for various emerging applications in the massive deployment of IoT devices due to lack of computing resources. In this paper, an energy- efficient AC computing methodology is proposed to facilitate lightweight encryption in RF powered devices such as RFIDs. Contrary to conventional methods that rely on rectification and regulation, the wirelessly harvested AC signal is directly used to drive the data processing circuity by leveraging charge- recycling mechanism. To quantify the advantages of the proposed framework, SIMON block cipher, a lightweight cryptography al- gorithm, is implemented in both AC computing and conventional methods. The simulation results demonstrate that the proposed methodology achieves up to 34 times reduction in power and enables a relatively powerful encryption core to be embedded within resource-constrained IoT devices. 

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2. Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications

   https://doi.org/10.1109/TC.2022.3174584  

   Ferdaus, Farah; Bahar Talukder, Bashir Mohammad; Rahman, Md Tauhidur (May 2022, IEEE Transactions on Computers)

   Approximate computing (AC) leverages the inherent error resilience and is used in many big-data applications from various domains such as multimedia, computer vision, signal processing, and machine learning to improve systems performance and power consumption. Like many other approximate circuits and algorithms, the memory subsystem can also be used to enhance performance and save power significantly. This paper proposes an efficient and effective systematic methodology to construct an approximate non-volatile magneto-resistive RAM (MRAM) framework using consumer-off-the-shelf (COTS) MRAM chips. In the proposed scheme, an extensive experimental characterization of memory errors is performed by manipulating the write latency of MRAM chips which exploits the inherent (intrinsic/extrinsic process variation) stochastic switching behavior of magnetic tunnel junctions (MTJs). The experimental results, involving error-resilient image compression and machine learning applications, reveal that the proposed AC framework provides a significant performance improvement and demonstrates a reduction in MRAM write energy of ~47.5% on average with negligible or no loss in output quality. 

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3. Split-Capacitor Boost Converter Operating in Boundary Conduction Mode with Impedance Matching for Kinetic Energy Harvesting

   https://doi.org/10.1109/MWSCAS48704.2020.9184507  

   Jaquan Dancy, Alante; Li, Jiayu; Sam Ha, Dong (August 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS))

   null (Ed.)

   The proposed circuit intends for an electromagnetic generator to harvest kinetic energy. A synchronous split-capacitor boost converter operating in boundary conduction mode (BCM) is proposed to efficiently convert the AC input to a DC output. BCM operation is uniquely achieved through zero current detection (ZCD) control of an AC input enabling impedance matching. The ZCD control offers simplicity over previously reported methodologies. To reduce power consumption and increase efficiency, the proposed circuit topology combines the rectifier and power stage while dynamically controlling the power stage. The proposed circuit is designed and laid out in 0.13 μm BiCMOS technology. Post layout simulations verify the operation of the proposed circuit. 

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4. DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs

   https://doi.org/10.1109/ICCD.2018.00078  

   Chen, Yuechen; Reza, Md Farhadur; Louri, Ahmed (October 2018, 2018 IEEE 36th International Conference on Computer Design)

   Network-on-Chips (NoCs) have emerged as the standard on-chip communication fabrics for multi/many core systems and system on chips. However, as the number of cores on chip increases, so does power consumption. Recent studies have shown that NoC power consumption can reach up to 40% of the overall chip power. Considerable research efforts have been deployed to significantly reduce NoC power consumption. In this paper, we build on approximate computing techniques and propose an approximate communication methodology called DEC-NoC for reducing NoC power consumption. The proposed DEC-NoC leverages applications' error tolerance and dynamically reduces the amount of error checking and correction in packet transmission, which results in a significant reduction in the number of retransmitted packets. The reduction in packet retransmission results in reduced power consumption. Our cycle accurate simulation using PARSEC benchmark suites shows that DEC-NoC achieves up to 56% latency reduction and up to 58% dynamic power reduction compared to NoC architectures with conventional error control techniques. 

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5. Accurately Simulating Energy Consumption of I/O-intensive Scientific Workflows

   https://doi.org/10.1007/978-3-030-22734-0_11  

   Ferreira da Silva, Rafael; Orgerie, Anne-Cecile; Casanova, Henri; Tanaka, Ryan; Deelman, Ewa; Suter, Frederic (July 2019, International Conference on Computational Science (ICCS))

   While distributed computing infrastructures can provide infrastructure-level techniques for managing energy consumption, application-level energy consumption models have also been developed to support energy-efficient scheduling and resource provisioning algorithms. In this work, we analyze the accuracy of a widely-used application-level model that have been developed and used in the context of scientific workflow executions. To this end, we profile two production scientific workflows on a distributed platform instrumented with power meters. We then conduct an analysis of power and energy consumption measurements. This analysis shows that power consumption is not linearly related to CPU utilization and that I/O operations significantly impact power, and thus energy, consumption. We then propose a power consumption model that accounts for I/O operations, including the impact of waiting for these operations to complete, and for concurrent task executions on multi-socket, multi-core compute nodes. We implement our proposed model as part of a simulator that allows us to draw direct comparisons between real-world and modeled power and energy consumption. We find that our model has high accuracy when compared to real-world executions. Furthermore, our model improves accuracy by about two orders of magnitude when compared to the traditional models used in the energy-efficient workflow scheduling literature. 

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