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1. OpenMP Kernel Language Extensions for Performance Portable GPU Codes

   Tian, Shilei; Scogland, Tom; Chapman, Barbara; Doerfert, Johannes (November 2023, Association for Computing Machinery)

   Badia, Rosa M; Mohror, Kathryn (Ed.)

   In contemporary high-performance computing architectures, the integration of GPU accelerators has become increasingly prevalent. To harness the full potential of these accelerators, developers often resort to vendor-specific kernel languages, such as CUDA. While this approach ensures optimal efficiency, it inherently compromises portability and engenders vendor dependency. Existing portable programming models, such as OpenMP, while promising, demand extensive code rewriting due to their foundamental difference from kernel languages. In this work, we introduce extensions to LLVM OpenMP, transforming it into a versatile and performance portable kernel language for GPU programming. These extensions allow for the seamless porting of programs from kernel languages to high-performance OpenMP GPU programs with minimal modifications. To evaluate our extension, we implemented a proof-of-concept prototype that contains a subset of extensions we proposed. We ported six established CUDA proxy and benchmark applications and evaluated their performance on both AMD and NVIDIA platforms. By comparing with native versions (HIP and CUDA), our results show that OpenMP, augmented with our extensions, can not only match but also in some cases exceed the performance of kernel languages, thereby offering performance portability with minimal effort from application developers. 

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2. Parallel Application Power and Performance Prediction Modeling Using Simulation

   https://doi.org/10.1109/WSC52266.2021.9715340  

   Ahmed, Kishwar; Yoshii, Kazutomo; Tasnim, Samia (December 2021, 2021 Winter Simulation Conference (WSC))

   High performance computing (HPC) system runs compute-intensive parallel applications requiring large number of nodes. An HPC system consists of heterogeneous computer architecture nodes, including CPUs, GPUs, field programmable gate arrays (FPGAs), etc. Power capping is a method to improve parallel application performance subject to variable power constraints. In this paper, we propose a parallel application power and performance prediction simulator. We present prediction model to predict application power and performance for unknown power-capping values considering heterogeneous computing architecture. We develop a job scheduling simulator based on parallel discrete-event simulation engine. The simulator includes a power and performance prediction model, as well as a resource allocation model. Based on real-life measurements and trace data, we show the applicability of our proposed prediction model and simulator. 

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3. UPIR: Toward the Design of Unified Parallel Intermediate Representation for Parallel Programming Models

   https://doi.org/10.1145/3559009.3569646  

   Wang, Anjia; Yi, Xinyao; Yan, Yonghong (October 2022, PACT '22: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques)

   The complexity of heterogeneous computing architectures, as well as the demand for productive and portable parallel application development, have driven the evolution of parallel programming models to become more comprehensive and complex than before. Enhancing the conventional compilation technologies and software infrastructure to be parallelism-aware has become one of the main goals of recent compiler development. In this work, we propose the design of unified parallel intermediate representation (UPIR) for multiple parallel programming models and for enabling unified compiler transformation for the models. UPIR specifies three commonly used parallelism patterns (SPMD, data and task parallelism), data attributes and explicit data movement and memory management, and synchronization operations used in parallel programming. We demonstrate UPIR via a prototype implementation in the ROSE compiler for unifying IR for both OpenMP and OpenACC and in both C/C++ and Fortran, for unifying the transformation that lowers both OpenMP and OpenACC code to LLVM runtime, and for exporting UPIR to LLVM MLIR dialect. The fully extended paper of this abstract can be found from https://arxiv.org/abs/2209.10643. 

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4. Exploring Parallel Computing with OpenMP on the Raspberry Pi

   https://doi.org/10.1145/3287324.3287535  

   Matthews, Suzanne J.; Adams, Joel C.; Brown, Richard A.; Shoop, Elizabeth (February 2019, Proceedings of the 50th ACM Technical Symposium on Computer Science Education (SIGCSE ’19))

   The ACM/IEEE CS 2013 report recommends fifteen hours of parallel & distributed computing (PDC) education for every undergraduate. This workshop illustrates the use of the Raspberry Pi as an inexpensive, multicore platform for teaching shared-memory parallel programming. The inexpensive and tactile nature of the Raspberry Pi enables each student to experience her own parallel multiprocessor through sight and touch. In this hands-on workshop, we will teach attendees how they can leverage the Raspberry Pi and the OpenMP library to teach shared-memory parallel concepts in their own classrooms. All CS educators who are interested in learning about the Raspberry Pi, shared memory parallelism, and OpenMP are encouraged to attend. In Part I of the workshop, each participant will connect to and learn about the Raspberry Pi's multicore capabilities. In Part II, each participant will engage in self-paced, hands-on exploration of basic parallel computing concepts using the OpenMP "patternlets" from CSinParallel.org. In Part III, participants will investigate more complex applications, such as numeric integration and drug design and study how these applications can be parallelized using OpenMP. We will conclude the workshop with a series of lightning talks discussing how the Raspberry Pi has been used to teach parallel computing concepts at different institutions. We will also present a summary of student perceptions of the Raspberry Pi. All materials from this workshop will be freely available from CSinParallel.org. Space is limited to 20 participants. A laptop is required. 

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5. MultiGrid on FPGA Using Data Parallel C++

   https://doi.org/10.1109/IPDPSW55747.2022.00147  

   Siefert, Christopher; Olivier, Stephen L.; Voskuilen, Gwendolyn; Young, Jeffrey (May 2022, IPDSPW)

   Centered on modern C++ and the SYCL standard for heterogeneous programming, Data Parallel C++ (dpc++) and Intel's oneAPI software ecosystem aim to lower the barrier to entry for the use of accelerators like FPGAs in diverse applications. In this work, we consider the usage of FPGAs for scientific computing, in particular with a multigrid solver, MueLu. We report on early experiences implementing kernels of the solver in DPC++ for execution on Stratix 10 FPGAs, and we evaluate several algorithmic design and implementation choices. These choices not only impact performance, but also shed light on the capabilities and limitations of DPC++ and oneAPI. 

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