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1. A Comparative Study of n- and p-Channel FeFETs with Ferroelectric HZO Gate Dielectric

   https://doi.org/10.3390/solids4040023  

   Jacob, Paul; Patil, Pooja C.; Deng, Shan; Ni, Kai; Sehra, Khushwant; Gupta, Mridula; Saxena, Manoj; MacMahon, David; Kurinec, Santosh (December 2023, Solids)

   This study investigates the electrical characteristics observed in n-channel and p-channel ferroelectric field effect transistor (FeFET) devices fabricated through a similar process flow with 10 nm of ferroelectric hafnium zirconium oxide (HZO) as the gate dielectric. The n-FeFETs demonstrate a faster complete polarization switching compared to the p-channel counterparts. Detailed and systematic investigations using TCAD simulations reveal the role of fixed charges and interface traps at the HZO-interfacial layer (HZO/IL) interface in modulating the subthreshold characteristics of the devices. A characteristic crossover point observed in the transfer characteristics of n-channel devices is attributed with the temporary switching between ferroelectric-based operation to charge-based operation, caused by the pinning effect due to the presence of different traps. This experimental study helps understand the role of charge trapping effects in switching characteristics of n- and p-channel ferroelectric FETs. 

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2. Reducing the Barrier Height in Organic Transistors

   https://doi.org/10.1002/aelm.202400503  

   Ghobadi, Arash; Mathai, Cherian_J; Cook, Jacob; Bian, Guang; Attar, Salahuddin; Al‐Hashimi, Mohammed; Gangopadhyay, Shubhra; Guha, Suchismita (October 2024, Advanced Electronic Materials)

   Abstract Reducing the Schottky barrier height and Fermi level de‐pinning in metal‐organic semiconductor contacts are crucial for enhancing the performance of organic transistors. The reduction of the Schottky barrier height in bottom‐contact top‐gate organic transistors is demonstrated by adding 1 nm thick atomic layer deposited Al₂O₃on the source and drain contacts. By using two different donor‐acceptor copolymers, bothp‐andn‐type transistors are investigated. Temperature‐dependent current–voltage measurements from non‐treated, self‐assembled monolayer treated, and Al₂O₃treated Au source‐drain contact field‐effect transistors with varying channel lengths are carried out. The drain current versus drain voltage near zero gate voltage, which may be described by the thermionic emission model at temperatures above 150 K, allows the estimation of the Schottky barrier height (φ_B). The Al₂O₃contact‐treated transistors show more than 40% lowerφ_Bcompared with the non‐treated contacts in thep‐type transistor. Similarly, an isoindigo‐based transistor, withn‐type transport, shows a reduction inφ_Bwith Al₂O₃treated contacts suggesting that such ultrathin oxide layers provide a universal method for reducing the barrier height. 

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3. Domain wall enabled steep slope switching in MoS2 transistors towards hysteresis-free operation

   https://doi.org/10.1038/s41699-022-00353-1  

   Song, Jingfeng; Qi, Yubo; Xiao, Zhiyong; Wang, Kun; Li, Dawei; Kim, Seung-Hyun; Kingon, Angus I.; Rappe, Andrew M.; Hong, Xia (November 2022, npj 2D Materials and Applications)

   Abstract The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS₂transistors back-gated by single-layer polycrystalline PbZr_0.35Ti_0.65O₃. The devices exhibit current switching ratios up to 8 × 10⁶within an ultra-low gate voltage window of$$V_{{{\mathrm{g}}}} = \pm \! 0.5$$ $V_g=\pm 0.5$V and subthreshold swing (SS) as low as 9.7 mV decade⁻¹at room temperature, transcending the 60 mV decade⁻¹Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics. 

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4. Mitigating Heavy Ion Irradiation‐Induced Degradation in p‐type SnO Thin‐Film Transistors at Room Temperature

   https://doi.org/10.1002/pssa.202300392  

   Al-Mamun, Nahid Sultan; Rasel, Md Abu Jafar; Wolfe, Douglas E.; Haque, Aman; Schoell, Ryan; Hattar, Khalid; Ryu, Seung Ho; Kim, Seong Keun (September 2023, physica status solidi (a))

   The study investigates the mitigation of radiation damage on p‐type SnO thin‐film transistors (TFTs) with a fast, room‐temperature annealing process. Atomic layer deposition is utilized to fabricate bottom‐gate TFTs of high‐quality p‐type SnO layers. After 2.8 MeV Au⁴⁺irradiation at a fluence level of 5.2 × 10¹² ions cm⁻², the output drain current and on/off current ratio (I_on/I_off) decrease by more than one order of magnitude, field‐effect mobility (μ_FE) reduces more than four times, and subthreshold swing (SS) increases more than four times along with a negative shift in threshold voltage. The observed degradation is attributed to increased surface roughness and defect density, as confirmed by scanning electron microscopy (SEM), high‐resolution micro‐Raman, and transmission electron microscopy (TEM) with geometric phase analysis (GPA). A technique is demonstrated to recover the device performance at room temperature and in less than a minute, using the electron wind force (EWF) obtained from low‐duty‐cycle high‐density pulsed current. At a pulsed current density of 4.0 × 10⁵ A cm⁻², approximately four times increase inI_on/I_offis observed, 41% increase inμ_FE, and 20% decrease in the SS of the irradiated TFTs, suggesting effectiveness of the new annealing technique. 

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5. Thin channel Ga2O3 MOSFET with 55 GHz fMAX and > 100 V breakdown

   https://doi.org/10.1063/5.0208580  

   Saha, Chinmoy Nath; Vaidya, Abhishek; Nipu, Noor Jahan; Meng, Lingyu; Yu, Dong Su; Zhao, Hongping; Singisetti, Uttam (August 2024, Applied Physics Letters)

   This Letter reports a highly scaled 90 nm gate length β-Ga2O3 (Ga2O3) T-gate MOSFET with a power gain cutoff frequency (fMAX) of 55 GHz. The 60 nm thin epitaxial Ga2O3 channel layer was grown by molecular beam epitaxy, while the highly doped (n++) source/drain regions were regrown using metal organic chemical vapor deposition. Maximum on current (IDS,MAX) of 160 mA/mm and trans-conductance (gm) around 36 mS/mm were measured at VDS = 10 V for LSD = 1.5 μm device. Transconductance and on current are limited by high channel sheet resistance (Rsheet). Gate/drain breakdown voltage of 125 V was measured for LGD = 1.2 μm. We extracted 27 GHz current gain cutoff frequency (fT) and 55 GHz fMAX for 20 V drain bias for unpassivated devices. While no current collapse was seen initially for both drain and gate lag measurements for 500 ns pulse, moderate current collapse was observed after DC, RF measurements caused by electrical stressing. We calculated a high fT. VBR product of 3.375 THz V, which is comparable to the state-of-the-art GaN HEMTs. This figure of merit suggests that Ga2O3 could be a potential candidate for X-band application. 

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