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1. Domain wall enabled steep slope switching in MoS2 transistors towards hysteresis-free operation

   https://doi.org/10.1038/s41699-022-00353-1  

   Song, Jingfeng ; Qi, Yubo ; Xiao, Zhiyong ; Wang, Kun ; Li, Dawei ; Kim, Seung-Hyun ; Kingon, Angus I. ; Rappe, Andrew M. ; Hong, Xia ( November 2022 , npj 2D Materials and Applications)

   The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS₂transistors back-gated by single-layer polycrystalline PbZr_0.35Ti_0.65O₃. The devices exhibit current switching ratios up to 8 × 10⁶within an ultra-low gate voltage window of$$V_{{{\mathrm{g}}}} = \pm \! 0.5$$$V_g=\pm 0.5$V and subthreshold swing (SS) as low as 9.7 mV decade⁻¹at room temperature, transcending the 60 mV decade⁻¹Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics.

    

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2. Mitigating Heavy Ion Irradiation‐Induced Degradation in p‐type SnO Thin‐Film Transistors at Room Temperature

   https://doi.org/10.1002/pssa.202300392  

   Al-Mamun, Nahid Sultan ; Rasel, Md Abu Jafar ; Wolfe, Douglas E. ; Haque, Aman ; Schoell, Ryan ; Hattar, Khalid ; Ryu, Seung Ho ; Kim, Seong Keun ( September 2023 , physica status solidi (a))

   The study investigates the mitigation of radiation damage on p‐type SnO thin‐film transistors (TFTs) with a fast, room‐temperature annealing process. Atomic layer deposition is utilized to fabricate bottom‐gate TFTs of high‐quality p‐type SnO layers. After 2.8 MeV Au⁴⁺irradiation at a fluence level of 5.2 × 10¹² ions cm⁻², the output drain current and on/off current ratio (I_on/I_off) decrease by more than one order of magnitude, field‐effect mobility (μ_FE) reduces more than four times, and subthreshold swing (SS) increases more than four times along with a negative shift in threshold voltage. The observed degradation is attributed to increased surface roughness and defect density, as confirmed by scanning electron microscopy (SEM), high‐resolution micro‐Raman, and transmission electron microscopy (TEM) with geometric phase analysis (GPA). A technique is demonstrated to recover the device performance at room temperature and in less than a minute, using the electron wind force (EWF) obtained from low‐duty‐cycle high‐density pulsed current. At a pulsed current density of 4.0 × 10⁵ A cm⁻², approximately four times increase inI_on/I_offis observed, 41% increase inμ_FE, and 20% decrease in the SS of the irradiated TFTs, suggesting effectiveness of the new annealing technique.

    

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3. SnSe/MoS 2 van der Waals Heterostructure Junction Field‐Effect Transistors with Nearly Ideal Subthreshold Slope

   https://doi.org/10.1002/adma.201902962  

   Guo, Jian ; Wang, Laiyuan ; Yu, Yiwei ; Wang, Peiqi ; Huang, Yu ; Duan, Xiangfeng ( October 2019 , Advanced Materials)

   The minimization of the subthreshold swing (SS) in transistors is essential for low‐voltage operation and lower power consumption, both critical for mobile devices and internet of things (IoT) devices. The conventional metal‐oxide‐semiconductor field‐effect transistor requires sophisticated dielectric engineering to achieve nearly ideal SS (60 mV dec⁻¹at room temperature). However, another type of transistor, the junction field‐effect transistor (JFET) is free of dielectric layer and can reach the theoretical SS limit without complicated dielectric engineering. The construction of a 2D SnSe/MoS₂van der Waals (vdW) heterostructure‐based JFET with nearly ideal SS is reported. It is shown that the SnSe/MoS₂vdW heterostructure exhibits excellent p–n diode rectifying characteristics with low saturate current. Using the SnSe as the gate and MoS₂as the channel, the SnSe/MoS₂vdW heterostructure exhibit well‐behavioured n‐channel JFET characteristics with a small pinch‐off voltageV_Pof −0.25 V, nearly ideal subthreshold swing SS of 60.3 mV dec⁻¹and high ON/OFF ratio over 10⁶, demonstrating excellent electronic performance especially in the subthreshold regime.

    

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4. A Comparative Study of n- and p-Channel FeFETs with Ferroelectric HZO Gate Dielectric

   https://doi.org/10.3390/solids4040023  

   Jacob, Paul ; Patil, Pooja C. ; Deng, Shan ; Ni, Kai ; Sehra, Khushwant ; Gupta, Mridula ; Saxena, Manoj ; MacMahon, David ; Kurinec, Santosh ( December 2023 , Solids)

   This study investigates the electrical characteristics observed in n-channel and p-channel ferroelectric field effect transistor (FeFET) devices fabricated through a similar process flow with 10 nm of ferroelectric hafnium zirconium oxide (HZO) as the gate dielectric. The n-FeFETs demonstrate a faster complete polarization switching compared to the p-channel counterparts. Detailed and systematic investigations using TCAD simulations reveal the role of fixed charges and interface traps at the HZO-interfacial layer (HZO/IL) interface in modulating the subthreshold characteristics of the devices. A characteristic crossover point observed in the transfer characteristics of n-channel devices is attributed with the temporary switching between ferroelectric-based operation to charge-based operation, caused by the pinning effect due to the presence of different traps. This experimental study helps understand the role of charge trapping effects in switching characteristics of n- and p-channel ferroelectric FETs.

    

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5. Record >10 MV/cm mesa breakdown fields in Al 0.85 Ga 0.15 N/Al 0.6 Ga 0.4 N high electron mobility transistors on native AlN substrates

   https://doi.org/10.1063/5.0083966  

   Khachariya, Dolar ; Mita, Seiji ; Reddy, Pramod ; Dangi, Saroj ; Dycus, J. Houston ; Bagheri, Pegah ; Breckenridge, M. Hayden ; Sengupta, Rohan ; Rathkanthiwar, Shashwat ; Kirste, Ronny ; et al ( April 2022 , Applied Physics Letters)

   The ultra-wide bandgap of Al-rich AlGaN is expected to support a significantly larger breakdown field compared to GaN, but the reported performance thus far has been limited by the use of foreign substrates. In this Letter, the material and electrical properties of Al 0.85 Ga 0.15 N/Al 0.6 Ga 0.4 N high electron mobility transistors (HEMT) grown on a 2-in. single crystal AlN substrate are investigated, and it is demonstrated that native AlN substrates unlock the potential for Al-rich AlGaN to sustain large fields in such devices. We further study how Ohmic contacts made directly to a Si-doped channel layer reduce the knee voltage and increase the output current density. High-quality AlGaN growth is confirmed via scanning transmission electron microscopy, which also reveals the absence of metal penetration at the Ohmic contact interface and is in contrast to established GaN HEMT technology. Two-terminal mesa breakdown characteristics with 1.3  μm separation possess a record-high breakdown field strength of ∼11.5 MV/cm for an undoped Al 0.6 Ga 0.4 N-channel layer. The breakdown voltages for three-terminal devices measured with gate-drain distances of 4 and 9  μm are 850 and 1500 V, respectively. 

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