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Title: Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs
A new reference-spur cancelation technique is presented for supply-regulated ring-oscillator-based integer-N phaselocked loops (PLLs). A passive RC filter is used to implement a feed-forward (FF) spur-coupling path to perform spur cancelation at the PLL control signal. The proposed technique achieves a simulated spur cancelation of about 22 dB at the first spur harmonic. The simulated postcancelation spur value is -79 dBc for an oscillator gain of 0.1 GHz/V and -46 dBc for an oscillator gain of 6 GHz/V. Spur cancelation is also robust against large process, voltage, and temperature variations in the gain and bandwidth of the FF path. A 1-GHz integerN PLL prototype in a 65-nm CMOS process has a measured cancelation of 19.5 and 13 dB at the first and the second spur harmonic, respectively, with 320 μW of total power consumption. The PLL prototype has an oscillator gain of 1.5 GHz/V, which results in a postcancelation spur of -53 dBc. The proposed zero-power technique is suitable for low-power PLLs as it achieves a large spur cancelation without requiring any additional power consumption or calibration.
Authors:
; ; ;
Award ID(s):
1705026
Publication Date:
NSF-PAR ID:
10057553
Journal Name:
IEEE transactions on very large scale integration (VLSI) systems
Volume:
26
Issue:
4
Page Range or eLocation-ID:
653-662
ISSN:
1063-8210
Sponsoring Org:
National Science Foundation
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