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1. Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration

   Miketic, Ivan; Salman, Emre (September 2020, IEEE International System-on-Chip Conference (SOCC))

   Charge-recycling adiabatic circuits are recently receiving increased attention due to both high energy-efficiency and higher resistance against side-channel attacks. These characteristics make adiabatic circuits a promising technique for Internet-of-things based applications. One of the important limitations of adiabatic logic is the higher intra-cell interconnect capacitance due to differential outputs and cross-coupled pMOS transistors. Since energy consumption has quadratic dependence on capacitance in adiabatic circuits (unlike conventional static CMOS where dependence is linear), higher interconnect capacitance significantly degrades the overall power savings that can be achieved by adiabatic logic, particularly in nanoscale technologies. In this paper, monolithic 3D integrated adiabatic circuits are introduced where transistor-level monolithic 3D technology is used to implement adiabatic gates. A 45 nm two-tier Mono3D PDK is used to demonstrate the proposed approach. Monolithic inter-tier vias are leveraged to significantly reduce parasitic interconnect capacitance, achieving up to 47% reduction in power-delay product as compared to 2D adiabatic circuits in a 45 nm technology node. 

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2. Disentangling the effects of non-adiabatic interactions upon ion self-diffusion within warm dense hydrogen

   https://doi.org/10.1098/rsta.2023.0034  

   Angermeier, William A.; Scheiner, Brett S.; Shaffer, Nathaniel R.; White, Thomas G. (August 2023, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences)

   Warm dense matter is a material state in the region of parameter space connecting condensed matter to classical plasma physics. In this intermediate regime, we investigate the significance of non-adiabatic electron-ion interactions upon ion dynamics. To disentangle non-adiabatic from adiabatic electron-ion interactions, we compare the ion self-diffusion coefficient from the non-adiabatic electron force field computational model with an adiabatic, classical molecular dynamics simulation. A classical pair potential developed through a force-matching algorithm ensures the only difference between the models is due to the electronic inertia. We implement this new method to characterize non-adiabatic effects on the self-diffusion of warm dense hydrogen over a wide range of temperatures and densities. Ultimately we show that the impact of non-adiabatic effects is negligible for equilibrium ion dynamics in warm dense hydrogen. This article is part of the theme issue ‘Dynamic and transient processes in warm dense matter’. 

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3. Counterdiabaticity and the quantum approximate optimization algorithm

   https://doi.org/10.22331/q-2022-01-27-635  

   Wurtz, Jonathan; Love, Peter J. (January 2022, Quantum)

   The quantum approximate optimization algorithm (QAOA) is a near-term hybrid algorithm intended to solve combinatorial optimization problems, such as MaxCut. QAOA can be made to mimic an adiabatic schedule, and in the p → ∞ limit the final state is an exact maximal eigenstate in accordance with the adiabatic theorem. In this work, the connection between QAOA and adiabaticity is made explicit by inspecting the regime of p large but finite. By connecting QAOA to counterdiabatic (CD) evolution, we construct CD-QAOA angles which mimic a counterdiabatic schedule by matching Trotter "error" terms to approximate adiabatic gauge potentials which suppress diabatic excitations arising from finite ramp speed. In our construction, these "error" terms are helpful, not detrimental, to QAOA. Using this matching to link QAOA with quantum adiabatic algorithms (QAA), we show that the approximation ratio converges to one at least as 1 − C ( p ) ∼ 1 / p μ . We show that transfer of parameters between graphs, and interpolating angles for p + 1 given p are both natural byproducts of CD-QAOA matching. Optimization of CD-QAOA angles is equivalent to optimizing a continuous adiabatic schedule. Finally, we show that, using a property of variational adiabatic gauge potentials, QAOA is at least counterdiabatic, not just adiabatic, and has better performance than finite time adiabatic evolution. We demonstrate the method on three examples: a 2 level system, an Ising chain, and the MaxCut problem. 

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4. Approximate Adiabatic Logic for Low-Power and Secure Edge Computing

   https://doi.org/10.1109/MCE.2021.3053908  

   Yang, Wu; Thapliyal, Himanshu (January 2021, IEEE Consumer Electronics Magazine)

   null (Ed.)

   Approximate computing is a promising approach for error-tolerant applications running on the Internet of Things (IoT) edge devices to reduce power consumption. However, approximate computation is susceptible to side-channel attacks, such as attacks based on differential power analysis (DPA). Energy efficiency could be further enhanced by applying adiabatic logic in approximate edge computing while increasing its protection against the side-channel attacks. As a case study, we are presenting two approximate adders based on adiabatic logic to illustrate the benefits of approximate computation combined with adiabatic logic. The proposed approximate adders leverage the dual-rail property of adiabatic logic to minimize the overall size and further decrease energy consumption. In this article, the first design is True Sum Approximate Adder (TSAA), while the second design is True Carry-out Approximate Adder (TCAA). There are fewer transistors in adiabatic logic-based TSAA and TCAA compared to CMOS based accurate mirror adder (AMA). At 12.5 MHz operating frequency and 45 nm technology node, the adiabatic TSAA and TCAA achieved power savings of 95.4% and 95.48%, energy savings of 90.80%, and 90.96% in comparison with the standard CMOS AMA. We also show that both designs proposed are more secure against DPA attacks. 

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5. Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices

   https://doi.org/10.1109/ISVLSI51109.2021.00064  

   Kahleifeh, Zachary; Thapliyal, Himanshu (July 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI))

   The tremendous growth in the number of Internet of Things (IoT) devices has increased focus on the energy efficiency and security of an IoT device. In this paper, we will present a design level, non-volatile adiabatic architecture for low-energy and Correlation Power Analysis (CPA) resistant IoT devices. IoT devices constructed with CMOS integrated circuits suffer from high dynamic energy and leakage power. To solve this, we look at both adiabatic logic and STT-MTJs (Spin Transfer Torque Magnetic Tunnel Junctions) to reduce both dynamic energy and leakage power. Furthermore, CMOS integrated circuits suffer from side-channel leakage making them insecure against power analysis attacks. We again look to adiabatic logic to design secure circuits with uniform power consumption, thus, defending against power analysis attacks. We have developed a hybrid adiabatic-MTJ architecture using two-phase adiabatic logic. We show that hybrid adiabatic-MTJ circuits are both low energy and secure when compared with CMOS circuits. As a case study, we have constructed one round of PRESENT and have shown energy savings of 64.29% at a frequency of 25 MHz. Furthermore, we have performed a correlation power analysis attack on our proposed design and determined that the key was kept hidden. 

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