- Publication Date:
- NSF-PAR ID:
- Journal Name:
- Applied Physics Express
- Sponsoring Org:
- National Science Foundation
More Like this
Record >10 MV/cm mesa breakdown fields in Al 0.85 Ga 0.15 N/Al 0.6 Ga 0.4 N high electron mobility transistors on native AlN substratesThe ultra-wide bandgap of Al-rich AlGaN is expected to support a significantly larger breakdown field compared to GaN, but the reported performance thus far has been limited by the use of foreign substrates. In this Letter, the material and electrical properties of Al 0.85 Ga 0.15 N/Al 0.6 Ga 0.4 N high electron mobility transistors (HEMT) grown on a 2-in. single crystal AlN substrate are investigated, and it is demonstrated that native AlN substrates unlock the potential for Al-rich AlGaN to sustain large fields in such devices. We further study how Ohmic contacts made directly to a Si-doped channel layer reduce the knee voltage and increase the output current density. High-quality AlGaN growth is confirmed via scanning transmission electron microscopy, which also reveals the absence of metal penetration at the Ohmic contact interface and is in contrast to established GaN HEMT technology. Two-terminal mesa breakdown characteristics with 1.3 μm separation possess a record-high breakdown field strength of ∼11.5 MV/cm for an undoped Al 0.6 Ga 0.4 N-channel layer. The breakdown voltages for three-terminal devices measured with gate-drain distances of 4 and 9 μm are 850 and 1500 V, respectively.
(Digital Presentation) Investigation of Top Electrodes Impact on Performance of Transparent Amorphous Indium Gallium Zinc Oxide (a-InGaZnO) Based Resistive Random Access MemoryThe traditional von Neumann architecture limits the increase in computing efficiency and results in massive power consumption in modern computers due to the separation of storage and processing units. The novel neuromorphic computation system, an in-memory computing architecture with low power consumption, is aimed to break the bottleneck and meet the needs of the next generation of artificial intelligence (AI) systems. Thus, it is urgent to find a memory technology to implement the neuromorphic computing nanosystem. Nowadays, the silicon-based flash memory dominates non-volatile memory market, however, it is facing challenging issues to achieve the requirements of future data storage device development due to the drawbacks, such as scaling issue, relatively slow operation speed, and high voltage for program/erase operations. The emerging resistive random-access memory (RRAM) has prompted extensive research as its simple two-terminal structure, including top electrode (TE) layer, bottom electrode (BE) layer, and an intermediate resistive switching (RS) layer. It can utilize a temporary and reversible dielectric breakdown to cause the RS phenomenon between the high resistance state (HRS) and the low resistance state (LRS). RRAM is expected to outperform conventional memory device with the advantages, notably its low-voltage operation, short programming time, great cyclic stability, and good scalability.more »
Ferroelectric transistor model based on self-consistent solution of 2D Poisson's, non-equilibrium Green's function and multi-domain Landau Khalatnikov equationsWe present a physics-based model for ferroelectric/negative capacitance transistors (FEFETs/ NCFETs) without an inter-layer metal between ferroelectric and dielectric in the gate stack. The model self-consistently solves 2D Poisson's equation, non-equilibrium Green's function (NEGF) based charge and transport equations, and multi-domain Landau Khalatnikov (LK) equations with the domain interaction term. The proposed simulation framework captures the variation of ferroelectric (FE) polarization (P) along the gate length due to non-uniform electric field (E) along the channel. To calibrate the LK equations, we fabricate and characterize 10nm HZO films. Based on the calibrated model, we analyze the gate/drain voltage dependence of P distribution in the FE and its effect on the channel potential and current-voltage characteristics. Our results highlight the importance of larger domain interaction to boost the benefits of FEFETs with subthreshold swing (SS) as small as ~50mV/decade achieved at room temperature. As domain interaction increases, the characteristics of FEFETs without inter-layer metal (SS, negative drain induced barrier lowering (DIBL), negative output conductance) approach those of FEFETs with inter-layer metal.
This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe2) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10–5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe2SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.
Strategies to Enhance the Capability of Carrier Injection to the Effective Channel for Bottom-gated Amorphous Oxide Thin Films TransistorsOver the two decades, amorphous oxide semiconductors (AOSs) and their thin film transistor (TFT) channel application have been intensely explored to realize high performance, transparent and flexible displays due to their high field effect mobility (μFE=5-20 cm2/Vs), visible range optical transparency, and low temperature processability (25-300 °C).[1-2] The metastable amorphous phase is to be maintained during operation by the addition of Zn and additional third cation species (e.g., Ga, Hf, or Al) as an amorphous phase stabilizer.[3-5] To limit TFT off-state currents, a thin channel layer (10-20 nm) was employed for InZnO (IZO)-based TFTs, or third cations were added to suppress carrier generations in the TFT channel. To resolve bias stress-induced instabilities in TFT performance, approaches to employ defect passivation layers or enhance channel/dielectric interfacial compatibility were demonstrated.[6-7] Metallization contact is also a dominating factor that determines the performance of TFTs. Particularly, it has been reported that high electrical contact resistance significantly sacrifices drain bias applied to the channel, which leads to undesirable power loss during TFT operation and issues for the measurement of TFT field effect mobilities. [2, 8] However, only a few reports that suggest strategies to enhance contact behaviors are available in the literature. Furthermore, the previousmore »