More Like this

1. Record >10 MV/cm mesa breakdown fields in Al _0.85 Ga _0.15 N/Al _0.6 Ga _0.4 N high electron mobility transistors on native AlN substrates

   https://doi.org/10.1063/5.0083966  

   Khachariya, Dolar ; Mita, Seiji ; Reddy, Pramod ; Dangi, Saroj ; Dycus, J. Houston ; Bagheri, Pegah ; Breckenridge, M. Hayden ; Sengupta, Rohan ; Rathkanthiwar, Shashwat ; Kirste, Ronny ; et al ( April 2022 , Applied Physics Letters)

   The ultra-wide bandgap of Al-rich AlGaN is expected to support a significantly larger breakdown field compared to GaN, but the reported performance thus far has been limited by the use of foreign substrates. In this Letter, the material and electrical properties of Al 0.85 Ga 0.15 N/Al 0.6 Ga 0.4 N high electron mobility transistors (HEMT) grown on a 2-in. single crystal AlN substrate are investigated, and it is demonstrated that native AlN substrates unlock the potential for Al-rich AlGaN to sustain large fields in such devices. We further study how Ohmic contacts made directly to a Si-doped channel layer reduce the knee voltage and increase the output current density. High-quality AlGaN growth is confirmed via scanning transmission electron microscopy, which also reveals the absence of metal penetration at the Ohmic contact interface and is in contrast to established GaN HEMT technology. Two-terminal mesa breakdown characteristics with 1.3  μm separation possess a record-high breakdown field strength of ∼11.5 MV/cm for an undoped Al 0.6 Ga 0.4 N-channel layer. The breakdown voltages for three-terminal devices measured with gate-drain distances of 4 and 9  μm are 850 and 1500 V, respectively.
2. (Digital Presentation) Investigation of Top Electrodes Impact on Performance of Transparent Amorphous Indium Gallium Zinc Oxide (a-InGaZnO) Based Resistive Random Access Memory

   https://doi.org/10.1149/MA2022-01191075mtgabs  

   Qin, Fei ; Lee, Sunghwan ( July 2022 , ECS Meeting Abstracts)

   The traditional von Neumann architecture limits the increase in computing efficiency and results in massive power consumption in modern computers due to the separation of storage and processing units. The novel neuromorphic computation system, an in-memory computing architecture with low power consumption, is aimed to break the bottleneck and meet the needs of the next generation of artificial intelligence (AI) systems. Thus, it is urgent to find a memory technology to implement the neuromorphic computing nanosystem. Nowadays, the silicon-based flash memory dominates non-volatile memory market, however, it is facing challenging issues to achieve the requirements of future data storage device development due to the drawbacks, such as scaling issue, relatively slow operation speed, and high voltage for program/erase operations. The emerging resistive random-access memory (RRAM) has prompted extensive research as its simple two-terminal structure, including top electrode (TE) layer, bottom electrode (BE) layer, and an intermediate resistive switching (RS) layer. It can utilize a temporary and reversible dielectric breakdown to cause the RS phenomenon between the high resistance state (HRS) and the low resistance state (LRS). RRAM is expected to outperform conventional memory device with the advantages, notably its low-voltage operation, short programming time, great cyclic stability, and good scalability.more »Among the materials for RS layer, indium gallium zinc oxide (IGZO) has shown attractive prospects in abundance and high atomic diffusion property of oxygen atoms, transparency. Additionally, its electrical properties can be easily modulated by controlling the stoichiometric ratio of indium and gallium as well as oxygen potential in the sputter gas. Moreover, since the IGZO can be applied to both the thin-film transistor (TFT) channel and RS layer, it has a great potential for fully integrated transparent electronics application. In this work, we proposed amorphous transparent IGZO-based RRAMs and investigated switching behaviors of the memory cells prepared with different top electrodes. First, ITO was choosing to serve as both TE and BE to achieve high transmittance. A multi-target magnetron sputtering system was employed to deposit all three layers (TE, RS, BE layers) on glass substrate. I-V characteristics were evaluated by a semiconductor parameter analyzer, and the bipolar RS feature of our RRAM devices was demonstrated by typical butterfly curves. The optical transmission analysis was carried out via a UV-Vis spectrometer and the average transmittance was around 80% out of entire devices in the visible-light wavelength range, implying high transparency. We adjusted the oxygen partial pressure during the sputtering of IGZO to optimize the property because the oxygen vacancy concentration governs the RS performance. Electrode selection is crucial and can impact the performance of the whole device. Thus, Cu TE was chosen for our second type of device because the diffusion of Cu ions can be beneficial for the formation of the conductive filament (CF). A ~5 nm SiO 2 barrier layer was employed between TE and RS layers to confine the diffusion of Cu into the RS layer. At the same time, this SiO 2 inserting layer can provide an additional interfacial series resistance in the device to lower the off current, consequently, improve the on/off ratio and whole performance. Finally, an oxygen affinity metal Ti was selected as the TE for our third type of device because the concentration of the oxygen atoms can be shifted towards the Ti electrode, which provides an oxygengettering activity near the Ti metal. This process may in turn lead to the formation of a sub-stoichiometric region in the neighboring oxide that is believed to be the origin of better performance. In conclusion, the transparent amorphous IGZO-based RRAMs were established. To tune the property of RS layer, the sputtering conditions of RS were varied. To investigate the influence of TE selections on switching performance of RRAMs, we integrated a set of TE materials, and a barrier layer on IGZO-based RRAM and compared the switch characteristics. Our encouraging results clearly demonstrate that IGZO is a promising material in RRAM applications and breaking the bottleneck of current memory technologies.« less
3. Ferroelectric transistor model based on self-consistent solution of 2D Poisson's, non-equilibrium Green's function and multi-domain Landau Khalatnikov equations

   https://doi.org/10.1109/IEDM.2017.8268385  

   Saha, A. K. ; Sharma, P. ; Dabo, I. ; Datta, S. ; Gupta, S. K. ( December 2017 , International Electron Device Meetings)

   We present a physics-based model for ferroelectric/negative capacitance transistors (FEFETs/ NCFETs) without an inter-layer metal between ferroelectric and dielectric in the gate stack. The model self-consistently solves 2D Poisson's equation, non-equilibrium Green's function (NEGF) based charge and transport equations, and multi-domain Landau Khalatnikov (LK) equations with the domain interaction term. The proposed simulation framework captures the variation of ferroelectric (FE) polarization (P) along the gate length due to non-uniform electric field (E) along the channel. To calibrate the LK equations, we fabricate and characterize 10nm HZO films. Based on the calibrated model, we analyze the gate/drain voltage dependence of P distribution in the FE and its effect on the channel potential and current-voltage characteristics. Our results highlight the importance of larger domain interaction to boost the benefits of FEFETs with subthreshold swing (SS) as small as ~50mV/decade achieved at room temperature. As domain interaction increases, the characteristics of FEFETs without inter-layer metal (SS, negative drain induced barrier lowering (DIBL), negative output conductance) approach those of FEFETs with inter-layer metal.
4. Improvements in 2D p-type WSe2 transistors towards ultimate CMOS scaling

   https://doi.org/10.1038/s41598-023-30317-4  

   Patoary, Naim Hossain ; Xie, Jing ; Zhou, Guantong ; Al Mamun, Fahad ; Sayyad, Mohammed ; Tongay, Sefaattin ; Esqueda, Ivan Sanchez ( February 2023 , Scientific Reports)

   This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe₂) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10^–5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe₂SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.
5. Strategies to Enhance the Capability of Carrier Injection to the Effective Channel for Bottom-gated Amorphous Oxide Thin Films Transistors

   Liu, Mingyuan ; Kim, Hyeonghun ; Song, Han Wook ; Lee, Sunghwan ( November 2021 , Materials Research Society)

   Over the two decades, amorphous oxide semiconductors (AOSs) and their thin film transistor (TFT) channel application have been intensely explored to realize high performance, transparent and flexible displays due to their high field effect mobility (μFE=5-20 cm2/Vs), visible range optical transparency, and low temperature processability (25-300 °C).[1-2] The metastable amorphous phase is to be maintained during operation by the addition of Zn and additional third cation species (e.g., Ga, Hf, or Al) as an amorphous phase stabilizer.[3-5] To limit TFT off-state currents, a thin channel layer (10-20 nm) was employed for InZnO (IZO)-based TFTs, or third cations were added to suppress carrier generations in the TFT channel. To resolve bias stress-induced instabilities in TFT performance, approaches to employ defect passivation layers or enhance channel/dielectric interfacial compatibility were demonstrated.[6-7] Metallization contact is also a dominating factor that determines the performance of TFTs. Particularly, it has been reported that high electrical contact resistance significantly sacrifices drain bias applied to the channel, which leads to undesirable power loss during TFT operation and issues for the measurement of TFT field effect mobilities. [2, 8] However, only a few reports that suggest strategies to enhance contact behaviors are available in the literature. Furthermore, the previousmore »approaches (1) require an additional fabrication complexity due to the use of additional treatments at relatively harsh conditions such as UV, plasma, or high temperatures, and (2) may lead to adverse effects on the channel material attributed to the chemical incompatibility between dissimilar materials, and exposures to harsh environments. Therefore, a simple and easy but effective buffer strategy, which does not require any additional process complexities and not sacrifice chemical compatibility, needs to be established to mitigate the contact issues and therefore achieve high performance and low power consumption AOS TFTs. The present study aims to demonstrate an approach utilizing an interfacial buffer layer, which is compositionally homogeneous to the channel to better align work functions between channel and metallization without a significant fabrication complexity and harsh treatment conditions. Photoelectron spectroscopic measurements reveal that the conducting IZO buffer, of which the work function (Φ) is 4.37 eV, relaxes a relatively large Φ difference between channel IZO (Φ=4.81 eV) and Ti (Φ=4.2-4.3 eV) metallization. The buffer is found to lower the energy barrier for charge carriers at the source to reach the effective channel region near the dielectric. In addition, the higher carrier density of the buffer and favorable chemical compatibility with the channel (compositionally the same) further contribute to a significant reduction in specific contact resistance as much as more than 2.5 orders of magnitude. The improved contact and carrier supply performance from the source to the channel lead to an enhanced field effect mobility of up to 56.49 cm2/Vs and a threshold voltage of 1.18 V, compared to 13.41 cm2/Vs and 7.44 V of IZO TFTs without a buffer. The present work is unique in that an approach to lower the potential barrier between the source and the effective channel region (located near the channel/dielectric interface, behaving similar to a buried-channel MOSFET [9]) by introducing a contact buffer layer that enhances the field effect mobility and facilitates carrier supply from the source to the effective channel region.« less