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1. Approximate Adiabatic Logic for Low-Power and Secure Edge Computing

   https://doi.org/10.1109/MCE.2021.3053908  

   Yang, Wu ; Thapliyal, Himanshu ( January 2021 , IEEE Consumer Electronics Magazine)

   null (Ed.)

   Approximate computing is a promising approach for error-tolerant applications running on the Internet of Things (IoT) edge devices to reduce power consumption. However, approximate computation is susceptible to side-channel attacks, such as attacks based on differential power analysis (DPA). Energy efficiency could be further enhanced by applying adiabatic logic in approximate edge computing while increasing its protection against the side-channel attacks. As a case study, we are presenting two approximate adders based on adiabatic logic to illustrate the benefits of approximate computation combined with adiabatic logic. The proposed approximate adders leverage the dual-rail property of adiabatic logic to minimize the overall size and further decrease energy consumption. In this article, the first design is True Sum Approximate Adder (TSAA), while the second design is True Carry-out Approximate Adder (TCAA). There are fewer transistors in adiabatic logic-based TSAA and TCAA compared to CMOS based accurate mirror adder (AMA). At 12.5 MHz operating frequency and 45 nm technology node, the adiabatic TSAA and TCAA achieved power savings of 95.4% and 95.48%, energy savings of 90.80%, and 90.96% in comparison with the standard CMOS AMA. We also show that both designs proposed are more secure against DPA attacks. 

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2. 2-SPGAL: 2-Phase Symmetric Pass Gate Adiabatic Logic for Energy-Efficient Secure Consumer IoT

   https://doi.org/10.1109/ICCE50685.2021.9427720  

   Degada, Amit ; Thapliyal, Himanshu ( January 2021 , 2021 IEEE International Conference on Consumer Electronics (ICCE))

   null (Ed.)

   The adaptation of the Internet-of-Things (IoT) for consumer electronics has enabled us to uplift everyday life. Low-power smart and secure computing devices are needed to sustain the expected growth of consumer IoT. Adiabatic switching is a modern approach that recycles the energy stored in load capacitance to save energy. Further, the cryptographic circuit designed using adiabatic switching is secure against the Correlation Power Analysis (CPA) attack in contrast to the same circuit designed using standard CMOS. In this paper, we propose 2-SPGAL, a 2-phase sinusoidal signal based clocking implementation of Symmetric Pass Gate Adiabatic Logic (SPGAL). As a case study, we simulated the design of PRESENT-80 (a lightweight cryptographic scheme) one round with an in-built Power Clock Generator (PCG) with 45nm technology. The 2-SPGAL shows on an average 82.76% and 67.35% better energy saving compared to standard CMOS, and 2-EE-SPFAL (another 2-phase adiabatic logic), respectively at a frequency range from 100 kHz to 25 MHz with a load of 1 fF. The 2-SPGAL has 16.78% savings of the number of transistors compared to 2-EE-SPFAL for implementation of one round PRESENT-80. Further, the CPA attacks reveal the key in standard CMOS, however, 2-SPGAL PRESENT-80 adiabatic logic design was successful to protect the key. 

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3. Magnetic Interconnects Based on Composite Multiferroics

   https://doi.org/10.3390/mi13111991  

   Khitun, Alexander ( November 2022 , Micromachines)

   The development of magnetic logic devices dictates a need for a novel type of interconnect for magnetic signal transmission. Fast signal damping is one of the problems which drastically differs from conventional electric technology. Here, we describe a magnetic interconnect based on a composite multiferroic comprising piezoelectric and magnetostrictive materials. Internal signal amplification is the main reason for using multiferroic material, where a portion of energy can be transferred from electric to magnetic domains via stress-mediated coupling. The utilization of composite multiferroics consisting of piezoelectric and magnetostrictive materials offers flexibility for the separate adjustment of electric and magnetic characteristics. The structure of the proposed interconnect resembles a parallel plate capacitor filled with a piezoelectric, where one of the plates comprises a magnetoelastic material. An electric field applied across the plates of the capacitor produces stress, which, in turn, affects the magnetic properties of the magnetostrictive material. The charging of the capacitor from one edge results in the charge diffusion accompanied by the magnetization change in the magnetostrictive layer. This enables the amplitude of the magnetic signal to remain constant during the propagation. The operation of the proposed interconnects is illustrated by numerical modeling. The model is based on the Landau–Lifshitz–Gilbert equation with the electric field-dependent anisotropy term included. A variety of magnetic logic devices and architectures can benefit from the proposed interconnects, as they provide reliable and low-energy-consuming data transmission. According to the estimates, the group velocity of magnetic signals may be up to 105 m/s with energy dissipation less than 10−18 J per bit per 100 nm. The physical limits and practical challenges of the proposed approach are also discussed. 

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4. Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices

   https://doi.org/10.1109/ISVLSI51109.2021.00064  

   Kahleifeh, Zachary ; Thapliyal, Himanshu ( July 2021 , 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI))

   The tremendous growth in the number of Internet of Things (IoT) devices has increased focus on the energy efficiency and security of an IoT device. In this paper, we will present a design level, non-volatile adiabatic architecture for low-energy and Correlation Power Analysis (CPA) resistant IoT devices. IoT devices constructed with CMOS integrated circuits suffer from high dynamic energy and leakage power. To solve this, we look at both adiabatic logic and STT-MTJs (Spin Transfer Torque Magnetic Tunnel Junctions) to reduce both dynamic energy and leakage power. Furthermore, CMOS integrated circuits suffer from side-channel leakage making them insecure against power analysis attacks. We again look to adiabatic logic to design secure circuits with uniform power consumption, thus, defending against power analysis attacks. We have developed a hybrid adiabatic-MTJ architecture using two-phase adiabatic logic. We show that hybrid adiabatic-MTJ circuits are both low energy and secure when compared with CMOS circuits. As a case study, we have constructed one round of PRESENT and have shown energy savings of 64.29% at a frequency of 25 MHz. Furthermore, we have performed a correlation power analysis attack on our proposed design and determined that the key was kept hidden. 

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5. High-Performance and Energy-Efficient 3D Manycore GPU Architecture for Accelerating Graph Analytics

   https://doi.org/10.1145/3482880  

   Choudhury, Dwaipayan ; Rajam, Aravind Sukumaran ; Kalyanaraman, Ananth ; Pande, Partha Pratim ( January 2022 , ACM Journal on Emerging Technologies in Computing Systems)

   Recent advances in GPU-based manycore accelerators provide the opportunity to efficiently process large-scale graphs on chip. However, real world graphs have a diverse range of topology and connectivity patterns (e.g., degree distributions) that make the design of input-agnostic hardware architectures a challenge. Network-on-Chip (NoC)- based architectures provide a way to overcome this challenge as the architectural topology can be used to approximately model the expected traffic patterns that emerge from graph application workloads. In this paper, we first study the mix of long- and short-range traffic patterns generated on-chip using graph workloads, and subsequently use the findings to adapt the design of an optimal NoC-based architecture. In particular, by leveraging emerging three-dimensional (3D) integration technology, we propose design of a small-world NoC (SWNoC)- enabled manycore GPU architecture, where the placement of the links connecting the streaming multiprocessors (SM) and the memory controllers (MC) follow a power-law distribution. The proposed 3D manycore GPU architecture outperforms the traditional planar (2D) counterparts in both performance and energy consumption. Moreover, by adopting a joint performance-thermal optimization strategy, we address the thermal concerns in a 3D design without noticeably compromising the achievable performance. The 3D integration technology is also leveraged to incorporate Near Data Processing (NDP) to complement the performance benefits introduced by the SWNoC architecture. As graph applications are inherently memory intensive, off-chip data movement gives rise to latency and energy overheads in the presence of external DRAM. In conventional GPU architectures, as the main memory layer is not integrated with the logic, off-chip data movement negatively impacts overall performance and energy consumption. We demonstrate that NDP significantly reduces the overheads associated with such frequent and irregular memory accesses in graph-based applications. The proposed SWNoC-enabled NDP framework that integrates 3D memory (like Micron's HMC) with a massive number of GPU cores achieves 29.5% performance improvement and 30.03% less energy consumption on average compared to a conventional planar Mesh-based design with external DRAM. 

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