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Receiver nonlinearity gives rise to intermodulation products that are caused by two strong adjacent channel signals called blockers. The nonlinear distortion effects are significantly higher for multiple antenna wideband systems in dispersive environments because third order intermodulation products decreases the signal-to-noise ratio (SNR) at the output of the equalization process. This complicates the demodulation process and increases the bit error rate. This paper considers such nonlinear distortion in the context of space-time shift keying (STSK)-enabled wideband single-carrier systems and proposes an iterative space-time block equalization (ISTBE) framework for frequency domain equalization. We present our design of a practical ISTBE receiver based on the turbo principle and numerically demonstrate that it effectively removes the residual inter-symbol interference while suppressing high-power blockers and the in-band intermodulation distortion that they cause. The proposed system is thus suitable for simple wideband radio frequency front ends operating in the weak nonlinear region and enables adjacent channel spectrum coexistence with heterogeneous transmitters and receivers of different qualities.
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Hardware Implementation of Single-carrier Time-domain Turbo Equalization for Severe Multipath Acoustic Communication Channels
This paper proposes a low-latency FPGA implemen-tation for Turbo equalization to combat very long multipathfading channels where the Intersymbol-interference (ISI) channellength is on the order of 100 taps. Turbo equalization is essentialfor such severe multipath channels, but exhibits very large latencyand high computational complexity due to its sequential anditerative data processing on large-scale matrix arithmetic. Thispaper proposes an FPGA acceleration architecture to exploitthe Hermitian symmetric property of the channel Gram matrixand convolutional nature of Sequential Interference Cancellation(SIC), and successfully implements a linear Turbo equalizerof 100 taps on a Xilinx Zynq UltraScale+ MPSoC ZCU102Evaluation Kit. The architecture is able to support two turboiterations for a 1024-symbol block size and achieve 200 kilo-symbols-per-second (ksps) transmission rate.
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- Award ID(s):
- 1853258
- PAR ID:
- 10208375
- Date Published:
- Journal Name:
- Ocean
- ISSN:
- 0197-7385
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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