This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.
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A Low-power Reconfigurable Readout Circuit with Large DC Offset Reduction for Neural Signal Recording Applications
This paper presents a fully reconfigurable readout circuit including a chopper-stabilized neural amplifier and a successive approximation register (SAR) analog-to-digital converter (ADC) for neural signal recording applications. Since the target neural signals - action potentials (APs) and local field potentials (LFPs) differ in the peak amplitude while occupying different frequency bandwidths, gain, and bandwidth reconfigurability would be advantageous in improving power and noise performance. The readout circuit is designed in 180 nm standard CMOS technology. It achieves the mid-band gain of 50.3 dB in the frequency band of 0.1 Hz - 250 Hz to detect the LFPs, and 63.4 dB in 267 Hz - 20.8 kHz for detecting the APs. The neural amplifier consumes a total power of 1.54 μW and 1.94 μW for LFP and AP configurations, respectively. The input-referred noises have been achieved as 0.97 μV rms (0.1 Hz - 250 Hz), and 0.44 μV rms (250 Hz - 5 kHz), leading to a noise efficiency factor (NEF) of 1.27 and 1.21, for the two configurations, respectively. It rejects the generated large DC offset up to 40 mV at the electrode-tissue interface, by implementing a DC servo loop (DSL). The offset voltage with the DSL becomes 0.23 mV, which is acceptable for the neural experiments. Enabling the impedance boosting loop, the DC input impedance is found to be within the range of 1.77 - 2.27 GΩ, introducing the reconfigurability in impedance for matching with the electrode impedance. The SAR-ADC having a varying sampling frequency ranging from 10 - 40 ksamples/s demonstrates to digitize the APs and the LFPs with the resolution from 8 - 10 bits. The entire AFE provides good compatibility to record the neural signal while lowering the large DC offset down to 0.23 mV.
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- Award ID(s):
- 1943990
- NSF-PAR ID:
- 10211207
- Date Published:
- Journal Name:
- 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)
- Page Range / eLocation ID:
- 521 to 524
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/MWSCAS48704.2020.9184526
