The BICEP/Keck Collaboration is currently leading the quest to the highest sensitivity measurements of the polarized CMB anisotropies on degree scale with a series of cryogenic telescopes, of which BICEP Array is the latest Stage-3 upgrade with a total of ∼32,000 detectors. The instrument comprises 4 receivers spanning 30 to 270 GHz, with the low-frequency 30/40 GHz deployed to the South Pole Station in late 2019. The full complement of receivers is forecast to set the most stringent constraints on the tensor to scalar ratio r. Building on these advances, the overarching small-aperture telescope concept is already being used as the reference for further Stage-4 experiment design.
In this paper I will present the development of the BICEP Array 150 GHz detector module and its fabrication requirements, with highlights on the high-density time division multiplexing (TDM) design of the cryogenic circuit boards. The low-impedance wiring required between the detectors and the first-stage SQUID amplifiers is crucial to maintain a stiff voltage bias on the detectors. A novel multi-layer FR4 Printed Circuit Board (PCB) with superconducting traces, capable of reading out up to 648 detectors, is presented along with its validation tests.
I will also describe an ultra-high density TDM detector module we developed for a CMB-S4-like experiment that allows up to 1,920 detectors to be read out. TDM has been chosen as the detector readout technology for the Cosmic Microwave Background Stage-4 (CMB-S4) experiment based on its proven low-noise performance, predictable costs and overall maturity of the architecture. The heritage for TDM is rooted in mm- and submm-wave experiments dating back 20 years and has since evolved to support a multiplexing factor of 64x in Stage-3 experiments.
more »
« less
Readout of a quantum processor with high dynamic range Josephson parametric amplifiers
We demonstrate a high dynamic range Josephson parametric amplifier (JPA) in which the active nonlinear element is implemented using an array of rf-SQUIDs. The device is matched to the 50 Ω environment with a Klopfenstein-taper impedance transformer and achieves a bandwidth of 250–300 MHz with input saturation powers up to −95 dBm at 20 dB gain. A 54-qubit Sycamore processor was used to benchmark these devices, providing a calibration for readout power, an estimation of amplifier added noise, and a platform for comparison against standard impedance matched parametric amplifiers with a single dc-SQUID. We find that the high power rf-SQUID array design has no adverse effect on system noise, readout fidelity, or qubit dephasing, and we estimate an upper bound on amplifier added noise at 1.6 times the quantum limit. Finally, amplifiers with this design show no degradation in readout fidelity due to gain compression, which can occur in multi-tone multiplexed readout with traditional JPAs.
more » « less- Award ID(s):
- 1747426
- NSF-PAR ID:
- 10479867
- Author(s) / Creator(s):
- ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; more »
- Publisher / Repository:
- AIP
- Date Published:
- Journal Name:
- Applied Physics Letters
- Volume:
- 122
- Issue:
- 1
- ISSN:
- 0003-6951
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
Millimeter wave (mmW) communications is viewed as the key enabler of 5G cellular networks due to vast spectrum availability that could boost peak rate and capacity. Due to increased propagation loss in mmW band, transceivers with massive antenna array are required to meet a link budget, but their power consumption and cost become limiting factors for commercial systems. Radio designs based on hybrid digital and analog array architectures and the usage of radio frequency (RF) signal processing via phase shifters have emerged as potential solutions to improve radio energy efficiency and deliver performances close to the conventional digital antenna arrays. In this paper, we provide an overview of the state-of-the-art mmW massive antenna array designs and comparison among three array architectures, namely digital array, partially-connected hybrid array (sub-array), and fully-connected hybrid array. The comparison of performance, power, and area for these three architectures is performed for three representative 5G downlink use cases, which cover a range of pre-beamforming signal-to-noise-ratios (SNR) and multiplexing regimes. This is the first study to comprehensively model and quantitatively analyze all design aspects and criteria including: 1) optimal linear precoder, 2) impact of quantization error in digital-to-analog converter (DAC) and phase shifters, 3) RF signal distribution network, 4) power and area estimation based on state-of-the-art mmW circuits including baseband digital precoding, digital signal distribution network, high-speed DACs, oscillators, mixers, phase shifters, RF signal distribution network, and power amplifiers. Our simulation results show that the fully-digital array architecture is the most power and area efficient compared against optimized designs for sub-array and hybrid array architectures. Our analysis shows that digital array architecture benefits greatly from multi-user multiplexing. The analysis also reveals that sub-array architecture performance is limited by reduced beamforming gain due to array partitioning, while the system bottleneck of the fully-connected hybrid architecture is the excessively complicated and power hungry RF signal distribution network.more » « less
-
null (Ed.)This paper presents a fully reconfigurable readout circuit including a chopper-stabilized neural amplifier and a successive approximation register (SAR) analog-to-digital converter (ADC) for neural signal recording applications. Since the target neural signals - action potentials (APs) and local field potentials (LFPs) differ in the peak amplitude while occupying different frequency bandwidths, gain, and bandwidth reconfigurability would be advantageous in improving power and noise performance. The readout circuit is designed in 180 nm standard CMOS technology. It achieves the mid-band gain of 50.3 dB in the frequency band of 0.1 Hz - 250 Hz to detect the LFPs, and 63.4 dB in 267 Hz - 20.8 kHz for detecting the APs. The neural amplifier consumes a total power of 1.54 μW and 1.94 μW for LFP and AP configurations, respectively. The input-referred noises have been achieved as 0.97 μV rms (0.1 Hz - 250 Hz), and 0.44 μV rms (250 Hz - 5 kHz), leading to a noise efficiency factor (NEF) of 1.27 and 1.21, for the two configurations, respectively. It rejects the generated large DC offset up to 40 mV at the electrode-tissue interface, by implementing a DC servo loop (DSL). The offset voltage with the DSL becomes 0.23 mV, which is acceptable for the neural experiments. Enabling the impedance boosting loop, the DC input impedance is found to be within the range of 1.77 - 2.27 GΩ, introducing the reconfigurability in impedance for matching with the electrode impedance. The SAR-ADC having a varying sampling frequency ranging from 10 - 40 ksamples/s demonstrates to digitize the APs and the LFPs with the resolution from 8 - 10 bits. The entire AFE provides good compatibility to record the neural signal while lowering the large DC offset down to 0.23 mV.more » « less
-
more » « less
We describe the newest generation of the SLAC Microresonator RF (SMuRF) electronics, a warm digital control and readout system for microwave-frequency resonator-based cryogenic detector and multiplexer systems, such as microwave superconducting quantum interference device multiplexers (μmux) or microwave kinetic inductance detectors. Ultra-sensitive measurements in particle physics and astronomy increasingly rely on large arrays of cryogenic sensors, which in turn necessitate highly multiplexed readout and accompanying room-temperature electronics. Microwave-frequency resonators are a popular tool for cryogenic multiplexing, with the potential to multiplex thousands of detector channels on one readout line. The SMuRF system provides the capability for reading out up to 3328 channels across a 4–8 GHz bandwidth. Notably, the SMuRF system is unique in its implementation of a closed-loop tone-tracking algorithm that minimizes RF power transmitted to the cold amplifier, substantially relaxing system linearity requirements and effective noise from intermodulation products. Here, we present a description of the hardware, firmware, and software systems of the SMuRF electronics, comparing achieved performance with science-driven design requirements. In particular, we focus on the case of large-channel-count, low-bandwidth applications, but the system has been easily reconfigured for high-bandwidth applications. The system described here has been successfully deployed in lab settings and field sites around the world and is baselined for use on upcoming large-scale observatories.
-
The design and characterization of a low noise amplifier optimized for the readout of microwave kinetic inductance detectors is described. The work is first motivated through a description of microwave kinetic inductance detectors and a discussion of the requirements for the low-noise amplifiers employed for readout of these devices. Next, the design of a two-stage silicon germanium cryogenic integrated circuit low noise amplifier is presented. The small-signal and large-signal characteristics of the fabricated amplifier are then measured. It is shown that, at a physical temperature of 16 K, the amplifier achieves a gain of greater than 30 dB and an average noise temperature of 3.3 K over the 0.4–1.2 GHz frequency band while dissipating less than 7 mW. Moreover, the wideband compression characteristics are measured it is found that the linearity of the amplifier is sufficient to support frequency domain multiplexed readout of more than 500 detectors.more » « less
- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1063/5.0127375
