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1. Multi-chip heterogeneously integrated array of active three-terminal transistor lasers and passive photonic structures for electronic-photonic integration on silicon

   https://doi.org/10.1117/12.2544009  

   Carlson, John A. ; Dallesasse, John M. ( February 2020 , Proceedings Volume 11285, Silicon Photonics XV)

   Reed, Graham T. ; Knights, Andrew P. (Ed.)

   An array of active photonic devices is fabricated in unison after a heterogeneous integration process first metal-eutectically bonds these distinct materials as a distribution onto a silicon host wafer. The patterning out of heterogeneous materials followed by the formation of all photonic devices allows for wide-area fine-alignment without the need for discrete die alignment or placement. The integration process is designed as a CMOS-compatible, scalable method for bringing together distinct III-V epitaxial structures and optical-waveguiding epitaxial structures, demonstrating the capabilities of forming a multi-chip layer of photonic materials. Integrated GaAs-based vertical light-emitting transistors (LET) are designed and fabricated as the active devices whose third electrical terminal provides an electrical interconnect and thermal dissipation path to the silicon host wafer. The performance of these devices as both electrical transistors and spontaneous-emission optical devices is compared to their monolithically-integrated counterparts to investigate improvements in device characteristics when integrated onto silicon. The fabrication methods are modified and optimized for thin-film transferred materials and are then extended to transistor laser (TL) fabrication. Passive waveguiding structures are designed and simulated for coupling light from the active devices, and their fabrication scheme is presented such that it can be similarly performed with transferred materials. Work toward the demonstration of integrated transistor lasers is shown to represent progress toward an electronic-photonic circuit network. The combination of heterogeneous integration with three-terminal photonic structures enables an elegant solution to both packaging and signal interconnect constraints for the implementation of photonic logic in silicon photonics systems. 

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2. Silicon nitride stress-optic microresonator modulator for optical control applications

   https://doi.org/10.1364/OE.467721  

   Wang, Jiawei ; Liu, Kaikai ; Harrington, Mark W. ; Rudy, Ryan Q. ; Blumenthal, Daniel J. ( August 2022 , Optics Express)

   Modulation-based control and locking of lasers, filters and other photonic components is a ubiquitous function across many applications that span the visible to infrared (IR), including atomic, molecular and optical (AMO), quantum sciences, fiber communications, metrology, and microwave photonics. Today, modulators used to realize these control functions consist of high-power bulk-optic components for tuning, sideband modulation, and phase and frequency shifting, while providing low optical insertion loss and operation from DC to 10s of MHz. In order to reduce the size, weight and cost of these applications and improve their scalability and reliability, modulation control functions need to be implemented in a low loss, wafer-scale CMOS-compatible photonic integration platform. The silicon nitride integration platform has been successful at realizing extremely low waveguide losses across the visible to infrared and components including high performance lasers, filters, resonators, stabilization cavities, and optical frequency combs. Yet, progress towards implementing low loss, low power modulators in the silicon nitride platform, while maintaining wafer-scale process compatibility has been limited. Here we report a significant advance in integration of a piezo-electric (PZT, lead zirconate titanate) actuated micro-ring modulation in a fully-planar, wafer-scale silicon nitride platform, that maintains low optical loss (0.03 dB/cm in a 625 µm resonator) at 1550 nm, with an order of magnitude increase in bandwidth (DC - 15 MHz 3-dB and DC - 25 MHz 6-dB) and order of magnitude lower power consumption of 20 nW improvement over prior PZT modulators. The modulator provides a >14 dB extinction ratio (ER) and 7.1 million quality-factor (Q) over the entire 4 GHz tuning range, a tuning efficiency of 162 MHz/V, and delivers the linearity required for control applications with 65.1 dB·Hz^2/3and 73.8 dB·Hz^2/3third-order intermodulation distortion (IMD3) spurious free dynamic range (SFDR) at 1 MHz and 10 MHz respectively. We demonstrate two control applications, laser stabilization in a Pound-Drever Hall (PDH) lock loop, reducing laser frequency noise by 40 dB, and as a laser carrier tracking filter. This PZT modulator design can be extended to the visible in the ultra-low loss silicon nitride platform with minor waveguide design changes. This integration of PZT modulation in the ultra-low loss silicon nitride waveguide platform enables modulator control functions in a wide range of visible to IR applications such as atomic and molecular transition locking for cooling, trapping and probing, controllable optical frequency combs, low-power external cavity tunable lasers, quantum computers, sensors and communications, atomic clocks, and tunable ultra-low linewidth lasers and ultra-low phase noise microwave synthesizers.

    

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3. Heterogeneous Integration for Silicon Photonic Systems: Challenges and Approaches

   https://doi.org/10.1109/EDTM50988.2021.9420896  

   Dallesasse, John M. ; Carlson, John A. ; Ganjoo, Manaav ; Espenhahn, Leah ( April 2021 , 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM))

   null (Ed.)

   Enhancing the functionality of silicon through the integration of other materials such as III-V semiconductors has been recognized as a path to overcoming limitations imposed by characteristics fundamental to silicon's material physics while still capitalizing on properties that have enabled the success of the global integrated circuit industry [1]–[2][3]. High-speed electronic devices, devices with high breakdown voltages, light emitting/detecting devices, and devices for photon control can all be integrated with conventional CMOS to perform specialized electronic or photonic functions if suitable methods for forming such heterogeneously integrated regions are available that provide high yield and are compatible with fabrication processes that occur subsequent to the heterogeneous integration process. Technical challenges include lattice mismatch, thermal expansion coefficient differences, having the capability to form low-resistance electrical contacts using materials that are compatible with CMOS, more generally managing cross-contamination in tools used for front-end-of-line processing after III-V regions are established on the silicon wafers, and thermal management for the heterogeneously integrated devices or circuits. These together create formidable obstacles, but there is also the obstacle of defining a business case for creating hybrid wafer fabs given the applications that would be served by ICs with enhanced functionality. Bringing functions that are off chip onto the chip needs to be justified both technically and financially. 

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4. Integrated lithium niobate electro-optic modulators: when performance meets scalability

   https://doi.org/10.1364/OPTICA.415762  

   Zhang, Mian ; Wang, Cheng ; Kharel, Prashanta ; Zhu, Di ; Lončar, Marko ( May 2021 , Optica)

   Electro-optic modulators (EOMs) convert signals from the electrical to the optical domain. They are at the heart of optical communication, microwave signal processing, sensing, and quantum technologies. Next-generation EOMs require high-density integration, low cost, and high performance simultaneously, which are difficult to achieve with established integrated photonics platforms. Thin-film lithium niobate (LN) has recently emerged as a strong contender owing to its high intrinsic electro-optic (EO) efficiency, industry-proven performance, robustness, and, importantly, the rapid development of scalable fabrication techniques. The thin-film LN platform inherits nearly all the material advantages from the legacy bulk LN devices and amplifies them with a smaller footprint, wider bandwidths, and lower power consumption. Since the first adoption of commercial thin-film LN wafers only a few years ago, the overall performance of thin-film LN modulators is already comparable with, if not exceeding, the performance of the best alternatives based on mature platforms such as silicon and indium phosphide, which have benefited from many decades of research and development. In this mini-review, we explain the principles and technical advances that have enabled state-of-the-art LN modulator demonstrations. We discuss several approaches, their advantages and challenges. We also outline the paths to follow if LN modulators are to improve further, and we provide a perspective on what we believe their performance could become in the future. Finally, as the integrated LN modulator is a key subcomponent of more complex photonic functionalities, we look forward to exciting opportunities for larger-scale LN EO circuits beyond single components.

    

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5. Robust Microfabrication of Highly Parallelized Three-Dimensional Microfluidics on Silicon

   https://doi.org/10.1038/s41598-019-48515-4  

   Yadavali, Sagar ; Lee, Daeyeon ; Issadore, David ( August 2019 , Scientific Reports)

   We present a new, robust three dimensional microfabrication method for highly parallel microfluidics, to improve the throughput of on-chip material synthesis by allowing parallel and simultaneous operation of many replicate devices on a single chip. Recently, parallelized microfluidic chips fabricated in Silicon and glass have been developed to increase the throughput of microfluidic materials synthesis to an industrially relevant scale. These parallelized microfluidic chips require large arrays (>10,000) of Through Silicon Vias (TSVs) to deliver fluid from delivery channels to the parallelized devices. Ideally, these TSVs should have a small footprint to allow a high density of features to be packed into a single chip, have channels on both sides of the wafer, and at the same time minimize debris generation and wafer warping to enable permanent bonding of the device to glass. Because of these requirements and challenges, previous approaches cannot be easily applied to produce three dimensional microfluidic chips with a large array of TSVs. To address these issues, in this paper we report a fabrication strategy for the robust fabrication of three-dimensional Silicon microfluidic chips consisting of a dense array of TSVs, designed specifically for highly parallelized microfluidics. In particular, we have developed a two-layer TSV design that allows small diameter vias (d < 20 µm) without sacrificing the mechanical stability of the chip and a patterned SiO₂etch-stop layer to replace the use of carrier wafers in Deep Reactive Ion Etching (DRIE). Our microfabrication strategy allows >50,000 (d = 15 µm) TSVs to be fabricated on a single 4” wafer, using only conventional semiconductor fabrication equipment, with 100% yield (M = 16 chips) compared to 30% using previous approaches. We demonstrated the utility of these fabrication strategies by developing a chip that incorporates 20,160 flow focusing droplet generators onto a single 4” Silicon wafer, representing a 100% increase in the total number of droplet generators than previously reported. To demonstrate the utility of this chip for generating pharmaceutical microparticle formulations, we generated 5–9 µm polycaprolactone particles with a CV < 5% at a rate as high as 60 g/hr (>1 trillion particles/hour).

    

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