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1. Multi-chip heterogeneously integrated array of active three-terminal transistor lasers and passive photonic structures for electronic-photonic integration on silicon

   https://doi.org/10.1117/12.2544009  

   Carlson, John A. ; Dallesasse, John M. ( February 2020 , Proceedings Volume 11285, Silicon Photonics XV)

   Reed, Graham T. ; Knights, Andrew P. (Ed.)

   An array of active photonic devices is fabricated in unison after a heterogeneous integration process first metal-eutectically bonds these distinct materials as a distribution onto a silicon host wafer. The patterning out of heterogeneous materials followed by the formation of all photonic devices allows for wide-area fine-alignment without the need for discrete die alignment or placement. The integration process is designed as a CMOS-compatible, scalable method for bringing together distinct III-V epitaxial structures and optical-waveguiding epitaxial structures, demonstrating the capabilities of forming a multi-chip layer of photonic materials. Integrated GaAs-based vertical light-emitting transistors (LET) are designed and fabricated as the active devices whose third electrical terminal provides an electrical interconnect and thermal dissipation path to the silicon host wafer. The performance of these devices as both electrical transistors and spontaneous-emission optical devices is compared to their monolithically-integrated counterparts to investigate improvements in device characteristics when integrated onto silicon. The fabrication methods are modified and optimized for thin-film transferred materials and are then extended to transistor laser (TL) fabrication. Passive waveguiding structures are designed and simulated for coupling light from the active devices, and their fabrication scheme is presented such that it can be similarly performed with transferred materials. Work toward the demonstration of integrated transistor lasers is shown to represent progress toward an electronic-photonic circuit network. The combination of heterogeneous integration with three-terminal photonic structures enables an elegant solution to both packaging and signal interconnect constraints for the implementation of photonic logic in silicon photonics systems. 

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2. BLAST: A Wafer‐Scale Transfer Process for Heterogeneous Integration of Optics and Electronics

   https://doi.org/10.1002/aelm.202300438  

   Ji, Yanxin ; Cortese, Alejandro J. ; Smart, Conrad L. ; Molnar, Alyosha C. ; McEuen, Paul L. ( November 2023 , Advanced Electronic Materials)

   A general transfer method is presented for the heterogeneous integration of different photonic and electronic materials systems and devices into a single substrate. Called BLAST, for Bond, Lift, Align, and Slide Transfer, the process works at wafer scale and offers precision alignment, high yield, varying topographies, and suitability for subsequent lithographic processing. BLAST's capabilities is demonstrated by integrating both GaAs and GaN µLEDs with silicon photovoltaics to fabricate optical wireless integrated circuits that up‐convert photons from the red to the blue. The study also shows that BLAST can be applied to a variety of other devices and substrates, including CMOS electronics, vertical cavity surface emitting lasers (VCSELs), and 2D materials. BLAST further enables the modularization of optoelectronic microsystems, where optical devices fabricated on one material substrate can be lithographically integrated with electronic devices on a different substrate in a scalable process.

    

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3. Towards Horizontal Heterojunctions for Tunnel Field Effect Transistors with Template Assisted Selective Epitaxy via MOCVD

   Brunelli, Simone ; Markman, B ; Wu, J ; Tseng, HY ; Goswami, A ; Rodwell, M ; Palmstrøm, P ; Klamkin, K ( June 2018 , International conference on MOVPE)

   Tunneling field effect transistors (TFETs) have gained much interest in the previous decade for use in low power CMOS electronics due to their sub-thermal switching [1]. To date, all TFETs are fabricated as vertical nanowires or fins with long, difficult processes resulting in long learning cycle and incompatibility with modern CMOS processing. Because most TFETs are heterojunction TFETs (HJ-TFETs), the geometry of the device is inherently vertically because dictated by the orientation of the tunneling HJ, achieved by typical epitaxy. Template assisted selective epitaxy was demonstrated for vertical nanowires [2] and horizontally arranged nanorods [3] for III-V on Si integration. In this work, we report results on the area selective and template assisted epitaxial growth of InP, utilizing SiO2 based confined structures on InP substrates, which enables horizontal HJs, that can find application in the next generation of TFET devices. The geometries of the confined structures used are so that only a small area of the InP substrate, dubbed seed, is visible to the growth atmosphere. Growth is initiated selectively only at the seed and then proceeds in the hollow channel towards the source hole. As a result, growth resembles epitaxial lateral overgrowth from a single nucleation point [4], reaping the benefits of defect confinement and, contrary to spontaneous nanowire growth, allows orientation in an arbitrary, template defined direction. Indium phosphide 2-inch (110) wafers are used as the starting substrate. The process flow (Fig.1) consists of two plasma enhanced chemical vapor deposition (PECVD) steps of SiO2, appropriately patterned with electron beam lithography (EBL), around a PECVD amorphous silicon sacrificial layer. The sacrificial layer is ultimately wet etched with XeF2 to form the final, channel like template. Not shown in the schematic in Fig.1 is an additional, ALD deposited, 3 nm thick, alumina layer which prevents plasma damage to the starting substrate and is removed via a final tetramethylammonium hydroxide (TMAH) based wet etch. As-processed wafers were then diced and loaded in a Thomas Swan Horizontal reactor. Successful growth conditions found were 600°C with 4E6 mol/min of group III precursor, a V/III ratio of 400 and 8 lpm of hydrogen as carrier gas. Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) were used as In and P precursors respectively. Top view SEM (Fig.2) confirms growth in the template thanks to sufficient Z-contrast despite the top oxide layer, not removed before imaging. TEM imaging shows a cross section of the confined structure taken at the seed hole (Fig.3). The initial growth interface suggests growth was initiated at the seed hole and atomic order of the InP conforms to the SiO2 template both at the seed and at the growth front. A sharp vertical facet is an encouraging result for the future development of vertical HJ based III-V semiconductor devices. 

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4. Heterogeneous Integration for Silicon Photonic Systems: Challenges and Approaches

   https://doi.org/10.1109/EDTM50988.2021.9420896  

   Dallesasse, John M. ; Carlson, John A. ; Ganjoo, Manaav ; Espenhahn, Leah ( April 2021 , 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM))

   null (Ed.)

   Enhancing the functionality of silicon through the integration of other materials such as III-V semiconductors has been recognized as a path to overcoming limitations imposed by characteristics fundamental to silicon's material physics while still capitalizing on properties that have enabled the success of the global integrated circuit industry [1]–[2][3]. High-speed electronic devices, devices with high breakdown voltages, light emitting/detecting devices, and devices for photon control can all be integrated with conventional CMOS to perform specialized electronic or photonic functions if suitable methods for forming such heterogeneously integrated regions are available that provide high yield and are compatible with fabrication processes that occur subsequent to the heterogeneous integration process. Technical challenges include lattice mismatch, thermal expansion coefficient differences, having the capability to form low-resistance electrical contacts using materials that are compatible with CMOS, more generally managing cross-contamination in tools used for front-end-of-line processing after III-V regions are established on the silicon wafers, and thermal management for the heterogeneously integrated devices or circuits. These together create formidable obstacles, but there is also the obstacle of defining a business case for creating hybrid wafer fabs given the applications that would be served by ICs with enhanced functionality. Bringing functions that are off chip onto the chip needs to be justified both technically and financially. 

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5. Heterogeneous Integration of Light-Emitting Transistors on Silicon for Hybrid Electronic-Photonic Logic Circuitry

   https://doi.org/10.1364/CLEO_AT.2019.JTh2A.60  

   Carlson, John A. ; Dallesasse, John M. ( January 2019 , Conference on Lasers and Electro-Optics, OSA Technical Digest)

   An array of heterogeneously integrated light-emitting transistors is fabricated after an epitaxial transfer process bonds and interconnects active III-V photonic material onto a CMOS- compatible host wafer for the purposes of establishing a photonic logic network. 

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