- Award ID(s):
- 1640196
- PAR ID:
- 10379670
- Editor(s):
- Choquette, Kent D.; Lei, Chun; Graham, Luke A.
- Date Published:
- Journal Name:
- Proceedings Volume 12020, Vertical-Cavity Surface-Emitting Lasers XXVI
- Volume:
- 12020
- Page Range / eLocation ID:
- 25
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
Reed, Graham T. ; Knights, Andrew P. (Ed.)An array of active photonic devices is fabricated in unison after a heterogeneous integration process first metal-eutectically bonds these distinct materials as a distribution onto a silicon host wafer. The patterning out of heterogeneous materials followed by the formation of all photonic devices allows for wide-area fine-alignment without the need for discrete die alignment or placement. The integration process is designed as a CMOS-compatible, scalable method for bringing together distinct III-V epitaxial structures and optical-waveguiding epitaxial structures, demonstrating the capabilities of forming a multi-chip layer of photonic materials. Integrated GaAs-based vertical light-emitting transistors (LET) are designed and fabricated as the active devices whose third electrical terminal provides an electrical interconnect and thermal dissipation path to the silicon host wafer. The performance of these devices as both electrical transistors and spontaneous-emission optical devices is compared to their monolithically-integrated counterparts to investigate improvements in device characteristics when integrated onto silicon. The fabrication methods are modified and optimized for thin-film transferred materials and are then extended to transistor laser (TL) fabrication. Passive waveguiding structures are designed and simulated for coupling light from the active devices, and their fabrication scheme is presented such that it can be similarly performed with transferred materials. Work toward the demonstration of integrated transistor lasers is shown to represent progress toward an electronic-photonic circuit network. The combination of heterogeneous integration with three-terminal photonic structures enables an elegant solution to both packaging and signal interconnect constraints for the implementation of photonic logic in silicon photonics systems.more » « less
-
null (Ed.)Enhancing the functionality of silicon through the integration of other materials such as III-V semiconductors has been recognized as a path to overcoming limitations imposed by characteristics fundamental to silicon's material physics while still capitalizing on properties that have enabled the success of the global integrated circuit industry [1]–[2][3]. High-speed electronic devices, devices with high breakdown voltages, light emitting/detecting devices, and devices for photon control can all be integrated with conventional CMOS to perform specialized electronic or photonic functions if suitable methods for forming such heterogeneously integrated regions are available that provide high yield and are compatible with fabrication processes that occur subsequent to the heterogeneous integration process. Technical challenges include lattice mismatch, thermal expansion coefficient differences, having the capability to form low-resistance electrical contacts using materials that are compatible with CMOS, more generally managing cross-contamination in tools used for front-end-of-line processing after III-V regions are established on the silicon wafers, and thermal management for the heterogeneously integrated devices or circuits. These together create formidable obstacles, but there is also the obstacle of defining a business case for creating hybrid wafer fabs given the applications that would be served by ICs with enhanced functionality. Bringing functions that are off chip onto the chip needs to be justified both technically and financially.more » « less
-
The heterogeneous integration of silicon with III-V materials provides a way to overcome silicon’s limited optical properties toward a broad range of photonic applications. Hybrid modes are a promising way to integrate such heterogeneous Si/III-V devices, but it remains unclear how to utilize these modes to achieve photonic crystal cavities. Herein, using 3D finite-difference time-domain simulations, we propose a hybrid Si-GaAs photonic crystal cavity design that operates at telecom wavelengths and can be fabricated without requiring careful alignment. The hybrid cavity consists of a patterned silicon waveguide that is coupled to a wider GaAs slab featuring InAs quantum dots. We show that by changing the width of the silicon cavity waveguide, we can engineer the hybrid modes and control the degree of coupling to the active material in the GaAs slab. This provides the ability to tune the cavity quality factor while balancing the device’s optical gain and nonlinearity. With this design, we demonstrate cavity mode confinement in the GaAs slab without directly patterning it, enabling strong interaction with the embedded quantum dots for applications such as low-power-threshold lasing and optical bistability (156 nW and 18.1
µ W, respectively). This heterogeneous integration of an active III-V material with silicon via a hybrid cavity design suggests a promising approach for achieving on-chip light generation and low-power nonlinear platforms. -
Chemicals are best recognized by their unique wavelength specific optical absorption signatures in the molecular fingerprint region from λ=3-15μm. In recent years, photonic devices on chips are increasingly being used for chemical and biological sensing. Silicon has been the material of choice of the photonics industry over the last decade due to its easy integration with silicon electronics as well as its optical transparency in the near-infrared telecom wavelengths. Silicon is optically transparent from 1.1 μm to 8 μm with research from several groups in the mid-IR. However, intrinsic material losses in silicon exceed 2dB/cm after λ~7μm (~0.25dB/cm at λ=6μm). In addition to the waveguiding core, an appropriate transparent cladding is also required. Available core-cladding choices such as Ge-GaAs, GaAs-AlGaAs, InGaAs-InP would need suspended membrane photonic crystal waveguide geometries. However, since the most efficient QCLs demonstrated are in the InP platform, the choice of InGaAs-InP eliminates need for wafer bonding versus other choices. The InGaAs-InP material platform can also potentially cover the entire molecular fingerprint region from λ=3-15μm. At long wavelengths, in monolithic architectures integrating lasers, detectors and passive sensor photonic components without wafer bonding, compact passive photonic integrated circuit (PIC) components are desirable to reduce expensive epi material loss in passive PIC etched areas. In this paper, we consider miniaturization of waveguide bends and polarization rotators. We experimentally demonstrate suspended membrane subwavelength waveguide bends with compact sub-50μm bend radius and compact sub-300μm long polarization rotators in the InGaAs/InP material system. Measurements are centered at λ=6.15μm for sensing ammoniamore » « less