Electromigration (EM) is still the most important reliability
concern for VLSI systems, especially at the nanometer regime. EM
immortality check is an important step for full-chip EM signoff
analysis. In this paper, we propose a new electromigration (EM)
immortality check method for multi-segment interconnect considering
the impacts of Joule heating induced temperature gradient.
Temperature gradients from metal Joule heating, called thermal
migration, can be a significant force for the metal atomic
migrations, and these impacts get more significant as technology
scales down. Compared to existing methods, the new method can
consider the spatial temperature gradient due to Joule heating for
multi-segment wires for the first time. We derive the analytic
solution for the resulting steady-state EM-thermal migration stress
distribution problem. Then we develop the new temperature-aware
voltage-based EM immortality check method considering the
multi-segment temperature migration effects, which carries all the
benefits of the recently proposed voltage-based EM immortality
method for multi-segment interconnects. Numerical results on an IBM
power grid and self synthesized power delivery networks show that
the proposed temperature-aware EM immortality check method is much
more accurate than recently proposed state of the art EM immortality
method.
more »
« less
GridNet: Fast date-driven EM-induced IR drop prediction and localized fixing for on-chip power grid networks
Electromigration (EM) is a major failure effect for on-chip power grid
networks of deep submicron VLSI circuits. EM degradation of metal grid
lines can lead to excessive voltage drops (IR drops) before the target
lifetime. In this paper, we propose a fast data-driven EM-induced IR
drop analysis framework for power grid networks, named {\it GridNet},
based on the conditional generative adversarial networks (CGAN). It
aims to accelerate the incremental full-chip EM-induced IR drop
analysis, as well as IR drop violation fixing during the power grid
design and optimization.
More importantly, {\it GridNet} can naturally leverage
the differentiable feature of deep neural networks (DNN) to {\it obtain the sensitivity
information of node voltage with respect to the wire resistance
(or width) with marginal cost}. {\it GridNet} treats continuous time
and the given electrical features as input conditions, and the
EM-induced time-varying voltage of power grid networks as the
conditional outputs, which are represented as data series images.
We show that {\it GridNet} is able to learn the temporal dynamics of
the aging process in continuous time domain.
Besides, we can take advantage of the sensitivity information provided
by {\it GridNet} to perform efficient localized IR drop
violation fixing in the late stage design and optimization.
Numerical results on 36000 synthesized power grid network samples
demonstrate that the new method can lead to $10^5\times$ speedup
over the recently proposed full-chip coupled EM and IR drop analysis
tool. We further show that localized IR drop violation fix for the
same set of power grid networks can be performed remarkably
efficiently using the cheap sensitivity computation from {\it GridNet}.
more »
« less
- NSF-PAR ID:
- 10279542
- Date Published:
- Journal Name:
- Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD’20),
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
This article presents a study of two types of on-chip FPGA voltage sensors based on ring oscillators (ROs) and time-to-digital converter (TDCs), respectively. It has previously been shown that these sensors are often used to extract side-channel information from FPGAs without physical access. The performance of the sensors is evaluated in the presence of circuits that deliberately waste power, resulting in localized voltage drops. The effects of FPGA power supply features and sensor sensitivity in detecting voltage drops in an FPGA power distribution network (PDN) are evaluated for Xilinx Artix-7, Zynq 7000, and Zynq UltraScale+ FPGAs. We show that both sensor types are able to detect supply voltage drops, and that their measurements are consistent with each other. Our findings show that TDC-based sensors are more sensitive and can detect voltage drops that are shorter in duration, while RO sensors are easier to implement because calibration is not required. Furthermore, we present a new time-interleaved TDC design that sweeps the sensor phase. The new sensor generates data that can reconstruct voltage transients on the order of tens of picoseconds.more » « less
-
This paper presents a new power grid network design and optimization technique that considers the new EM immortality constraint due to EM void saturation volume for multi-segment interconnects. Void may grow to its saturation volume without changing the wire resistance significantly. However, this phenomenon was ignored in existing EM-aware optimization methods. By considering this new effect, we can remove more conservativeness in the EM-aware on-chip power grid design. Along with recently proposed nucleation phase immortality constraint for multi-segment wires, we show that both EM immortality constraints can be naturally integrated into the existing programming based power grid optimization framework. To further mitigate the overly conservative problem of existing immortality-constrained optimization methods, we further explore two strategies: first we size up failed wires to meet one of immorality conditions subject to design rules; second, we consider the EM-induced aging effects on power supply networks for a targeted lifetime, which allows some short-lifetime wires to fail and optimizes the rest of the wires. Numerical results on a number of IBM and self-generated power supply networks demonstrate that the new method can reduce more power grid area compared to the existing EM-immortality constrained optimizations. Furthermore, the new method can optimize power grids with nucleated wires, which would not be possible with the existing methods.more » « less
-
Abstract We present a novel photonic chip design for high bandwidth four-degree optical switches that support high-dimensional switching mechanisms with low insertion loss and low crosstalk in a low power consumption level and a short switching time. Such four-degree photonic chips can be used to build an integrated full-grid Photonic-on-Chip Network (PCN). With four distinct input/output directions, the proposed photonic chips are superior compared to the current bidirectional photonic switches, where a conventionally sizable PCN can only be constructed as a linear chain of bidirectional chips. Our four-directional photonic chips are more flexible and scalable for the design of modern optical switches, enabling the construction of multi-dimensional photonic chip networks that are widely applied for intra-chip communication networks and photonic data centers. More noticeably, our photonic networks can be self-controlling with our proposed Multi-Sample Discovery model, a deep reinforcement learning model based on Proximal Policy Optimization. On a PCN, we can optimize many criteria such as transmission loss, power consumption, and routing time, while preserving performance and scaling up the network with dynamic changes. Experiments on simulated data demonstrate the effectiveness and scalability of the proposed architectural design and optimization algorithm. Perceivable insights make the constructed architecture become the self-controlling photonic-on-chip networks.more » « less
-
Electromigration (EM) analysis for complicated interconnects requires the solving of partial differential equations, which is expensive. In this paper, we propose a fast transient hydrostatic stress analysis for EM failure assessment for multi-segment interconnects using generative adversarial networks (GANs). Our work is inspired by the image synthesis and feature of generative deep neural networks. The stress evaluation of multi-segment interconnects, modeled by partial differential equations, can be viewed as time-varying 2D-images-to-image problem where the input is the multi-segment interconnects topology with current densities and the output is the EM stress distribution in those wire segments at the given aging time. We show that the conditional GAN can be exploited to attend the temporal dynamics for modeling the time-varying dynamic systems like stress evolution over time. The resulting algorithm, called {\it EM-GAN}, can quickly give accurate stress distribution of a general multi-segment wire tree for a given aging time, which is important for full-chip fast EM failure assessment. Our experimental results show that the EM-GAN shows 6.6\% averaged error compared to COMSOL simulation results with orders of magnitude speedup. It also delivers $8.3 \times$ speedup over state-of-the-art analytic based EM analysis solver.more » « less
- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Conference Paper:
- The DOI is not currently available.
