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1. Memristive devices with short-term and long-term memory behaviors for processing temporal information

   https://doi.org/10.1063/5.0175200  

   Ki, Seung Jun; Kim, Jisoo; Chen, Mingze; Liang, Xiaogan (November 2023, Applied Physics Letters)

   Memristors based on 2D semiconductors such as MoS2 and its derivative materials exhibit analog switching behaviors capable of emulating some synaptic functions, including short-term plasticity, long-term potentiation, and spike-time-dependent-plasticity. Additional investigation is needed to realize reliable control of such synaptic behaviors for practical device implementation. To meet this scientific need, we fabricated MoS2-based memristors and studied their paired-pulse facilitation (PPF) and long-term memory characteristics under different pulse programming settings. This research has provided a guideline for identifying the programming settings for different neuromorphic processes. For example, a specific setting resulting in PPF > 30% and long-term conductance change < 20% has been identified to be suited for processing real-time temporal information. Furthermore, this research also indicates that the MoS2 memristor keeps having an almost constant relative change in conductance but greatly enhanced drive current level under laser illumination. This behavior can enable an easy integration of such memristive devices with state-of-the-art controller circuits for practice neuromorphic control applications. 

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2. An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM

   https://doi.org/10.1109/ISLPED.2019.8824944  

   Yuan, Geng; Ma, Xiaolong; Ding, Caiwen; Lin, Sheng; Zhang, Tianyun; Jalali, Zeinab S.; Zhao, Yilong; Jiang, Li; Soundarajan, Sucheta; Wang, Yanzhi (January 2019, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED))

   The high computation and memory storage of large deep neural networks (DNNs) models pose intensive challenges to the conventional Von-Neumann architecture, incurring substantial data movements in the memory hierarchy. The memristor crossbar array has emerged as a promising solution to mitigate the challenges and enable low-power acceleration of DNNs. Memristor-based weight pruning and weight quantization have been separately investigated and proven effectiveness in reducing area and power consumption compared to the original DNN model. However, there has been no systematic investigation of memristor-based neuromorphic computing (NC) systems considering both weight pruning and weight quantization. In this paper, we propose an unified and systematic memristor-based framework considering both structured weight pruning and weight quantization by incorporating alternating direction method of multipliers (ADMM) into DNNs training. We consider hardware constraints such as crossbar blocks pruning, conductance range, and mismatch between weight value and real devices, to achieve high accuracy and low power and small area footprint. Our framework is mainly integrated by three steps, i.e., memristor- based ADMM regularized optimization, masked mapping and retraining. Experimental results show that our proposed frame- work achieves 29.81× (20.88×) weight compression ratio, with 98.38% (96.96%) and 98.29% (97.47%) power and area reduction on VGG-16 (ResNet-18) network where only have 0.5% (0.76%) accuracy loss, compared to the original DNN models. We share our models at anonymous link http://bit.ly/2Jp5LHJ . 

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3. Post-Manufacture Criticality-Aware Gain Tuning of Timing Encoded Spiking Neural Networks for Yield Recovery

   https://doi.org/10.1109/ETS61313.2024.10567479  

   Saha, Anurup; Ma, Kwondo; Amarnath, Chandramouli; Chatterjee, Abhijit (May 2024, IEEE)

   Time-to-first-spike(TTFS ) encoded spiking neural networks (SNNs), implemented using memristive crossbar arrays (MCA), achieve higher inference speed and energy efficiency compared to artificial neural networks (ANNs) and rate encoded SNNs. However, memristive crossbar arrays are vulnerable to conductance variations in the embedded memristor cells. These degrade the performance of TTFS encoded SNNs, namely their classification accuracy with adverse impact on the yield of manufactured chips. To combat this yield loss, we propose a post-manufacture testing and tuning framework for these SNNs. In the testing phase, a timing encoded signature of the SNN, which is statistically correlated to the SNN performance, is extracted. In the tuning phase, this signature is mapped to optimal values of the tuning knobs (gain parameters), one parameter per layer, using a trained regressor, allowing very fast tuning (about 150ms). To further reduce the tuning overhead, we rank order hidden layer neurons based on their criticality and show that adding gain programmability only to 50% of the neurons is sufficient for performance recovery. Experiments show that the proposed framework can improve yield by up to 34% and average accuracy of memristive SNNs by up to 9%. 

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4. Post-Manufacture Criticality-Aware Gain Tuning of Timing Encoded Spiking Neural Networks for Yield Recovery,

   Saha, A; Ma, K; Amarnath, A; Chatterjee, A (May 2025, IEEE)

   Time-to-first-spike (TTFS) encoded spiking neural networks (SNNs), implemented using memristive crossbar arrays (MCA), achieve higher inference speed and energy efficiency compared to artificial neural networks (ANNs) and rate encoded SNNs. However, memristive crossbar arrays are vulnerable to conductance variations in the embedded memristor cells. These degrade the performance of TTFS encoded SNNs, namely their classification accuracy, with adverse impact on the yield of manufactured chips. To combat this yield loss, we propose a postmanufacture testing and tuning framework for these SNNs. In the testing phase, a timing encoded signature of the SNN, which is statistically correlated to the SNN performace, is extracted. In the tuning phase, this signature is mapped to optimal values of the tuning knobs (gain parameters), one parameter per layer, using a trained regressor, allowing very fast tuning (about 150ms). To further reduce the tuning overhead, we rank order hidden layer neurons based on their criticality and show that adding gain programmability only to 50% of the neurons is sufficient for performance recovery. Experiments show that the proposed framework can improve yield by up to 34% and average accuracy of memristive SNNs by up to 9%. 

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5. Timing Selector: Using Transient Switching Dynamics to Solve the Sneak Path Issue of Crossbar Arrays

   https://doi.org/10.1002/smsc.202100072  

   Rao, Mingyi; Song, Wenhao; Kiani, Fatemeh; Asapu, Shiva; Zhuo, Ye; Midya, Rivu; Upadhyay, Navnidhi; Wu, Qing; Barnell, Mark; Lin, Peng; et al (October 2021, Small Science)

   Sneak path current is a fundamental issue and a major roadblock to the wide application of memristor crossbar arrays. Traditional selectors such as transistors compromise the 2D scalability and 3D stack‐ability of the array, while emerging selectors with highly nonlinear current–voltage relations contradict the requirement of a linear current–voltage relation for efficient multiplication by directly using Ohm's law. Herein, the concept of a timing selector is proposed and demonstrated, which addresses the sneak path issue with a voltage‐dependent delay time of its transient switching behavior, while preserving a linear current–voltage relationship for computation. Crossbar arrays with silver‐based diffusive memristors as the timing selectors are built and the operation principle and operational windows are experimentally demonstrated. The timing selector enables large memristor crossbar arrays that can be used to solve large‐dimension real‐world problems in machine intelligence and neuromorphic computing. 

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