Silicon carbide (SiC) MOSFET features low switching loss and it is advantageous in high switching frequency application, but the manufacture per Ampere cost is approximately five times higher than the silicon (Si) IGBT. Therefore, by paralleling Si IGBT and SiC MOSFET together, a trade-off between cost and loss is achieved. In this paper, a four control freedoms active gate driver (AGD) including turn-on delay, turn-off delay, and two independent gate voltages, is proposed to optimize the performance of the paralleled device. By adjusting these four control freedoms, optimal operation for paralleled device can be obtained. Moreover, the proposed AGD can dynamically adjust the current ratio between two paralleled devices, which can help achieve thermal balance between two devices and improve system reliability. Double pulse test (DPT) experimental results are presented and analyzed to validate the effectiveness of the proposed AGD for paralleled Si IGBT and SiC MOSFET application.
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Multi-level Active Gate Driver for SiC MOSFETs with Paralleling Operation
Abstract—Wide band gap (WBG) devices, like silicon carbide (SiC) MOSFET has gradually replaced the traditional silicon counterpart due to their advantages of high operating temperature and fast switching speed. Paralleling operations of SiC MOSFETs are unavoidable in high power applications in order to meet the system current requirement. However, parasitics mismatches among different paralleling devices would cause current unbalance issues, which would reduce the system reliability and maximum current capability. Thus, to achieve current balancing operation, this paper proposes a
solution of using multi-level active gate driver, where the dynamic current sharing during turn-on and turn-off processes are achieved by adjusting the delays, intermediate turn-on and turn-off voltages. The static current sharing is maintained by regulating the static turn-on gate voltage, where the on-state resistance mismatch between different devices can be
compensated. A double pulse test setup with two different SiC MOSFETs is built to emulate the scenario of worst case application with large differences of threshold voltage and on-state resistance. The experimental results demonstrate that the proposed active gate driver can achieve both dynamic and static current sharing operations for SiC MOSFETs with paralleling operation. Moreover, the system control diagram is discussed. Simulation studies are conducted to achieve closed-loop control of the paralleled SiC MOSFETs with the aid of the active gate driver approach.
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- Award ID(s):
- 1939144
- NSF-PAR ID:
- 10317623
- Date Published:
- Journal Name:
- IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL)IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL)
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/COMPEL52922.2021.9645994
