skip to main content
US FlagAn official website of the United States government
dot gov icon
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
https lock icon
Secure .gov websites use HTTPS
A lock ( lock ) or https:// means you've safely connected to the .gov website. Share sensitive information only on official, secure websites.


Title: Application Driven Rapid Synthesis for Analog BIST Components
This work proposes rapid synthesis of analog builtin self-test (BIST) circuits using a streamlined design methodology that pulls BIST circuit architecture(s) from a library of components and synthesizes the circuit(s) using a circuit-level design automation (DA) algorithm that combines Multivariate Regression models with Geometric Programming optimization. The presented design methodology is verified through the design of two current-sense BIST circuits for insertion into two different DC-DC converter applications. For each of the two experimental cases, a topology is automatically selected for BIST current sensing, and then the BIST circuit is rapidly sized using the presented DA algorithm.  more » « less
Award ID(s):
1943271
PAR ID:
10343378
Author(s) / Creator(s):
; ;
Date Published:
Journal Name:
IEEE International Midwest Symposium on Circuits and Systems
Page Range / eLocation ID:
1-4
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. This work proposes a novel design automation (DA) technique that uses a multifaceted approach combining Multivariate Regression with Geometric Programming (GP) to design analog circuits. Previous DA methods employing GP have typically used analytical derivations of the various design equations representing an analog circuit. The proposed DA method eliminates the need for analytical derivations by using simulation data and multivariate regression to generate statistical models combined with GP to solve these statistical expressions with respect to optimum circuit design parameters. This presented statistical GP method has been applied to successfully design a five-transistor two-stage operational amplifier and a folded cascode amplifier in a TSMC 65nm CMOS technology. The presented statistical GP DA results are comparable to the design results obtained from both analytical GP 
    more » « less
  2. Abstract Josephson-CMOS hybrid memory leverages the high speed and low power operation of single-flux quantum logic and the high integration densities of CMOS technology. One of the commonly used type of interface circuits in Josephson-CMOS memory is a Suzuki stack, which is a latching high-voltage driver circuit. Suzuki stack circuits are typically powered by an AC bias voltage that has several limitations such as synchronization and coupling effects. To address these issues, a novel DC-biased Suzuki stack circuit is proposed in this paper. As compared to a conventional AC-biased Suzuki stack circuit, the proposed DC-biased design can provide similar output voltage levels and parameter margins, approximately two times higher operating frequency, and three orders of magnitude lower heat load of bias cables. 
    more » « less
  3. null (Ed.)
    This paper presents a circuit for simultaneous reception of optical power and data using a solar cell. The circuit employs a switched-inductor boost DC-DC converter for energy harvesting and a low-power thresholding receiver for data reception. The thresholding data receiver comprises a current-sense resistor that monitors the current output of the solar cell, an instrumentation amplifier, a band-pass filter and a comparator. A system-level analysis of an optical communication system employing the proposed circuit is presented along with a circuit-level analysis and implementation. As a proof-of-concept, the proposed circuit for simultaneous power and data reception is implemented using off-the-shelf components and tested using a custom-built test setup. Measurement results, including harvested power, electronic noise and bit error rate (BER), are reported for a GaAs solar cell and a red LED light source. Results show that 223 μW of power are harvested by the DC-DC converter at a distance of 32.5 cm and a radiated power of 9.3 mW. At a modulation depth of 50% and a transmission speed of 2.5 kbps, a BER of 1.008×10^-3 is achieved. Measurement results reveal that the proposed solution exhibits a trade-off between harvested power, transmission speed and BER. 
    more » « less
  4. This paper demonstrates a high-efficiency modular multilevel resonant DC-DC converter (MMRC) with zero-voltage switching (ZVS) capability. In order to minimize the conduction loss in the converter, optimizing the root-mean-square (RMS) current flowing through switching devices is considered an effective approach. The analysis of circuit configuration and operating principle show that the RMS value of the current flowing through switching devices is closely related to the factors such as the resonant tank parameters, switching frequency, converter output voltage and current, etc. A quantitative analysis that considers all these factors has been performed to evaluate the RMS current of all the components in the circuit. When the circuit parameters are carefully designed, the switch current waveform can be close to the square waveform, which has a low RMS value and results in low conduction loss. And a design example based on the theoretical analysis is presented to show the design procedures of the presented converter. A 600 W 48 V-to-12 V prototype is built with the parameters obtained from the design example section. Simulation and experiments have been performed to verify the high-efficiency feature of the designed converter. The measured converter peak efficiency reaches 99.55% when it operates at 200 kHz. And its power density can be as high as 795 W/in 3 . 
    more » « less
  5. In this paper, an approach is described for enhancing the security of analog circuits using Satisfiability Modulo theory (SMT) based design space exploration. The technique takes as inputs generic circuit equations and performance constraints and, by exhaustively exploring the design space, outputs transistor sizes that satisfy the given constraints. The analog satisfiability (aSAT) methodology is applied to parameter biasing obfuscation, where the width of a transistor is obfuscated to mask circuit properties, while also limiting the number of keys that produce the target performance requirements. The proposed methodology is used in the design of a differential amplifier and a two stage amplifier. The widths determined through aSAT analysis are shown to meet the gain, phase margin, and power consumption requirements for both a differential amplifier and a two-stage amplifier. However, a 7 MHz offset in the gain-bandwidth of the two-stage amplifier is observed from the target value of 30 MHz. The total gain of the two stage amplifier is masked with a 24 bit encryption key that results in a probability of 5.96x10-08 to determine the correct key. The simulated results indicate that the proposed analog design methodology quickly and accurately determines transistor sizes for target specifications, while also accounting for obfuscation of analog circuit parameters. 
    more » « less