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The self-interference (SI) channels in full-duplex (FD) radios have large nano-second-scale delay spreads, which poses a significant challenge in designing SI cancelers that can emulate the SI channel over wide bandwidths. Passive implementations of high delay lines have a prohibitively large form factor and loss when implemented on silicon, whereas active implementations suffer from noise and linearity penalties. In this work, we leverage time-interleaved multi-path switched-capacitor (SC) circuits to provide large wideband delays with a small form factor and low power (LP) consumption to implement RF and baseband (BB) cancelers in an FD receiver (RX). We utilize capacitor stacking to obtain passive voltage gain to compensate for the loss of these delay elements, thus permitting an increased number of interleaved paths and, hence, a higher delay. Furthermore, to reduce the RX noise figure (NF) penalty due to injecting the cancellation signal into the receiver, we introduce a novel low-noise trans-impedance amplifier (LNTA) architecture, which injects the cancellation signal into RX and also accomplishes finite impulse response (FIR) filter weighting and summation. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 0.1 to 1 GHz. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging
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Stochastic Computing-based Baseband Processing for Resource Constraint IoT Devices
With the recent deployment of 5G network, the ever increasing IoT has got a tremendous boost in its expansion and already has penetrated well into the government, commercial and private sectors. With the countless IoT devices and myriad of applications, many of them are resource constrained and have limited energy budget. These IoT devices demand low-energy technique for their computing and communication tasks to stay active for longer period. The two main baseband processes that dissipate bulk of CPU power from the IoT device are synchronization and Finite Impulse Response (FIR) filtering. In this circumstance, hardware-based baseband processing can take these tasks off of the CPU and may significantly reduce energy consumption. While conventional Binary Radix Computing (BC)-based hardware modules can improve power dissipation, Stochastic Computing (SC)-based hardware will certainly cut down much more both the power as well as silicon space in comparison. With this motivation, we propose novel SC-based hardware designs in regards to synchronization and Finite Impulse Response (FIR) filter for resource constraint IoT devices. Comparative analysis shows that our proposed SC-based design can reduce significantly more power and silicon area compared to the BC as well as other proposed SC designs.
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- Award ID(s):
- 2029295
- PAR ID:
- 10349758
- Date Published:
- Journal Name:
- INCoS-2022
- Volume:
- 527
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1007/978-3-031-14627-5_3
